# US 9,437,561 B2 · Semiconductor chip with redundant thru-silicon-vias

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,561 B2
- Document ID: US9437561B2
- Status: Granted
- Kind: B2
- Application number: 12/878,542
- Filed: 2010-09-09
- Published: 2012-03-15
- Granted: 2016-09-06
- Earliest claimed: 2010-09-09
- Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Applicants: Bryan Black; Michael Z. Su; Gamal Refai-Ahmed; Joe Siegel; Seth Prejean
- Inventors: Bryan Black; Michael Z. Su; Gamal Refai-Ahmed; Joe Siegel; Seth Prejean
- Web page: https://patentgrep.com/patent/US9437561B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2125: {Top-view shapes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/07254: {changes in dispositions}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

## Claims

### Claim 1

A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends;
forming conductive via extensions on each of the first ends of the first conductive vias; and
forming a first conductor pad in ohmic contact with the conductive via extensions.

### Claim 2 (depends on 1)

The method of claim 1, comprising forming a second plurality of conductive vias in the layer, the second plurality of conductive vias including third ends and fourth ends, and forming a second conductor pad in ohmic contact with the third ends.

### Claim 3 (depends on 1)

The method of claim 1, comprising forming a conductor structure in ohmic contact with the second ends of the first plurality of conductive vias.

### Claim 4 (depends on 3)

The method of claim 3, wherein the conductor structure comprises a redistribution layer structure.

### Claim 5 (depends on 1)

The method of claim 1, comprising coupling an input/out structure to the first conductor pad.

### Claim 6 (depends on 5)

The method of claim 5, wherein the input/output structure comprises a solder bump or a conductive pillar.

### Claim 7 (depends on 1)

The method of claim 1, comprising stacking a second semiconductor chip on the first semiconductor chip.

### Claim 8 (depends on 1)

The method of claim 1, comprising mounting the first semiconductor chip on a circuit board.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first plurality of conductive vias are formed by forming trenches in the first semiconductor chip and placing conductor material in the trenches.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.

### Claim 11

A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends, the first semiconductor chip having a first side and a second and opposite side;
forming conductive via extensions on each of the first ends of the first conductive vias;
forming a first conductor structure proximate the first side and in ohmic contact with the conductive via extensions; and
forming a second conductor proximate the second side and in ohmic contact with the second ends of the first plurality of conductive vias.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first conductor comprises a conductor pad and the second conductor comprises a redistribution layer structure.

### Claim 13 (depends on 11)

The method of claim 11, comprising coupling an input/output structure to the first conductor.

### Claim 14 (depends on 13)

The method of claim 13, wherein the input/output structure comprises a solder bump or a conductive pillar.

### Claim 15 (depends on 11)

The method of claim 11, comprising stacking a second semiconductor chip on the first semiconductor chip.

### Claim 16 (depends on 11)

The method of claim 11, wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.

### Claim 17

A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends, second ends, a polymer core and a conductor jacket around the polymer core; and
forming a first conductor pad in ohmic contact with the first ends of the first conductive vias.