# US 9,437,560 B2 · Semiconductor device including landing pad

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- Number: US 9,437,560 B2
- Document ID: US9437560B2
- Status: Granted
- Kind: B2
- Application number: 14/606,245
- Filed: 2015-01-27
- Published: 2015-07-30
- Granted: 2016-09-06
- Earliest claimed: 2014-01-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Je-min Park; Yoo-sang Hwang
- Web page: https://patentgrep.com/patent/US9437560B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/482: {Bit lines}
- H10W 72/90: Bond pads, in general
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate that has an active area;
a pair of conductive line structures on the substrate and including insulating spacer structures respectively formed on side walls thereof;
a contact plug between the pair of conductive line structures and connected to the active area;
a first insulating pattern on the pair of conductive line structures;
a second insulating pattern to contact a side surface of the first insulating pattern and a top surface of each of the insulating spacer structures; and
a landing pad connected to the contact plug, formed between the first insulating pattern and the second insulating pattern, and extending to and over the first insulating pattern to vertically overlap one conductive line structure of the pair of conductive line structures.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a capacitor lower electrode on a top surface of the landing pad to be electrically connected to the landing pad.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
a top surface of the first insulating pattern is substantially parallel to a plane that extends from a main surface of the substrate, and
a bottom surface of the first insulating pattern covering top surfaces of the insulating spacer structure and the pair of conductive line structures in a direction substantially parallel to the plane that extends from the main surface of the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein:
the contact plug between the pair of conductive line structures has a width of a first size in a direction substantially parallel to a plane that extends from a main surface of the substrate;
the landing pad has a width of a second size over the first insulating pattern in the direction parallel to the plane that extends from the main surface of the substrate; and
the second size is greater than the first size.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a metal silicide film between the contact plug and the landing pad.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first insulating pattern and the second insulating pattern include a same material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the insulating spacer structure includes an air spacer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising
a barrier film to surround side walls of the first insulating pattern, the second insulating pattern, and the insulating spacer structure.

### Claim 9

A semiconductor device, comprising:
an active area;
adjacent conductive lines in a layer over the active area;
an insulating spacer between the conductive lines and defining a contact hole having a first width in a first direction;
a first insulating pattern on the conductive lines and insulating spacer;
a second insulating pattern over the first insulating pattern to define a landing pad hole, the second insulating pattern having a second width different from the first width;
a contact plug in the contact hole and connected to the active area; and
a landing pad in the landing pad hole and connected to the contact plug, wherein the landing pad or the contact plug at least partially overlaps one of the conductive lines along the first direction.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, further comprising:
a capacitor electrode electrically connected to the landing pad.

### Claim 11 (depends on 9)

The semiconductor device as claimed in claim 9, wherein the second width is greater than the first width.