# US 9,437,557 B2 · High density three-dimensional integrated capacitors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,557 B2 - Document ID: US9437557B2 - Status: Granted - Kind: B2 - Application number: 14/934,544 - Filed: 2015-11-06 - Published: 2016-03-17 - Granted: 2016-09-06 - Earliest claimed: 2010-12-09 - Assignees: Tessera, Inc. - Applicants: Tessera, Inc. - Inventors: Ilyas Mohammed; Belgacem Haba; Cyprian Emeka Uzoh; Piyush Savalia; Vage Oganesian - Web page: https://patentgrep.com/patent/US9437557B2 ## CPC - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H01G 4/06: Solid dielectrics - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching} - H10D 1/68: Capacitors having no potential barriers - H10D 1/716: {having vertical extensions} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2128: {Coaxial through-semiconductor vias} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 44/212: {Coaxial feed-throughs in substrates} - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. ## Claims ### Claim 1 A method of fabricating a component having electrodes for electrical interconnection with a circuit component or microelectronic element, comprising: removing material from a first surface of a substrate consisting essentially of a material having an effective CTE of less than 10 ppm/° C. to form a plurality of first openings extending from the first surface towards a second surface opposite the first surface, the first openings defining an undulating inner surface; forming a capacitor dielectric layer overlying the inner surface, the capacitor dielectric layer having an undulating first surface facing away from the inner surface; forming a first metal element overlying the first surface of the capacitor dielectric layer and extending into each of the first openings; removing material from the second surface of the substrate, such that a thickness of the substrate between the first and second surfaces is reduced; removing material of the substrate between adjacent ones of the plurality of first openings so as to expose an undulating second surface of the capacitor dielectric layer to form a plurality of second openings extending from the second surface towards the first surface; and forming a second metal element overlying the second surface of the capacitor dielectric layer and extending into each of the second openings. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein the step of forming the capacitor dielectric layer is performed by aqueous plating of a flowable dielectric material onto the inner surface exposed within each first opening. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the step of removing material from the second surface of the substrate is performed before the step of removing material of the substrate between adjacent ones of the plurality of first openings. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein at least one of the first and second metal elements is a metal layer that conforms to a contour of a surface of the capacitor dielectric layer. ### Claim 5 (depends on 4) The method as claimed in claim 4, wherein each of the first and second metal elements has a first portion that is separated from an adjacent second portion that is substantially parallel to the first portion by a dielectric material. ### Claim 6 (depends on 1) The method as claimed in claim 1, further comprising forming a first electrode connected to the first metal element and a second electrode connected to the second metal element, the first and second electrodes being exposed at the respective first and second surfaces, the first and second electrodes being connectable to respective first and second electric potentials. ### Claim 7 A method of fabricating a component having electrodes for electrical interconnection with a circuit component or microelectronic element, comprising: forming a plurality of first openings extending from a first surface of a substrate towards a second surface opposite the first surface, the first openings arranged to occupy at least some positions in an m×n array of positions, each of m and n being greater than 1, each first opening extending into the through opening in a vertical direction substantially perpendicular to the first surface, the plurality of first openings defining an inner surface, each first opening having a width in a horizontal plane substantially perpendicular to the vertical direction of 5 microns or less; forming a first capacitor dielectric layer overlying a first portion of the inner surface, the first capacitor dielectric layer having a first surface facing away from the inner surface; forming a first metal element having a plurality of posts, each post overlying the first surface of the first capacitor dielectric layer and extending into a corresponding opening of the first openings; removing material of the substrate between adjacent ones of the first subset of the plurality of posts so as to expose a second surface of the first capacitor dielectric layer to form a second opening extending from the second surface towards the first surface; and forming a second metal element overlying the second surface of the first capacitor dielectric layer and extending into the second opening. ### Claim 8 (depends on 7) The method as claimed in claim 7, wherein the substrate has an effective CTE of less than 10 ppm/° C. ### Claim 9 (depends on 7) The method as claimed in claim 7, wherein a first plurality of the posts extend into a first subset of the first openings located at a first plurality of positions within the m×n array, further comprising depositing an insulating dielectric material into a second subset of the first openings located at a second plurality of positions within the m×n array. ### Claim 10 (depends on 7) The method as claimed in claim 7, wherein the plurality of posts extends into all of the first openings. ### Claim 11 (depends on 7) The method as claimed in claim 7, wherein the first openings are formed by removing material from the first surface to form a plurality of pores. ### Claim 12 (depends on 7) The method as claimed in claim 7, wherein the substrate comprises a silicon material, and wherein the step of forming the plurality of first openings is performed by anisotropic etching, such that a region of porous silicon is produced extending from the first surface of the substrate. ### Claim 13 (depends on 7) The method as claimed in claim 7, wherein the step of forming the plurality of first openings is performed such that the length of each first opening is at least 150 microns. ### Claim 14 (depends on 7) The method as claimed in claim 7, wherein the step of forming the plurality of first openings is performed such that the first openings define a pitch in the horizontal plane of 10 microns or less. ### Claim 15 (depends on 7) The method as claimed in claim 7, wherein the step of forming the first capacitor dielectric layer is performed by aqueous plating of a flowable dielectric material onto the first portion of the inner surface. ### Claim 16 (depends on 7) The method as claimed in claim 7, further comprising, before the step of removing material of the substrate between adjacent ones of the first subset of the first openings, removing material from the second surface of the substrate, such that a thickness of the substrate between the first and second surfaces is reduced. ### Claim 17 (depends on 7) The method as claimed in claim 7, wherein the step of forming the first metal element is performed such that each post includes a substantially vertical portion that is substantially parallel to a corresponding substantially vertical portion of at least one adjacent post. ### Claim 18 (depends on 7) The method as claimed in claim 7, wherein at least one of the first and second metal elements is a metal layer that conforms to a contour of a surface of the capacitor dielectric layer. ### Claim 19 (depends on 18) The method as claimed in claim 18, wherein each of the first and second metal elements has a first portion that is separated from an adjacent second portion that is substantially parallel to the first portion by a dielectric material. ### Claim 20 (depends on 7) The method as claimed in claim 7, further comprising forming a first electrode connected to the first metal element and a second electrode connected to the second metal element, the first and second electrodes being exposed at the respective first and second surfaces, the first and second electrodes being connectable to respective first and second electric potentials.