# US 9,437,555 B2 · Semiconductor device having features to prevent reverse engineering

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- Number: US 9,437,555 B2
- Document ID: US9437555B2
- Status: Granted
- Kind: B2
- Application number: 14/504,868
- Filed: 2014-10-02
- Published: 2016-04-07
- Granted: 2016-09-06
- Earliest claimed: 2011-06-07
- Assignees: Verisiti, Inc.
- Applicants: Verisiti, Inc.
- Inventors: William Eli Thacker, III
- Web page: https://patentgrep.com/patent/US9437555B2

## CPC

- H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering
- G05F 3/205: {Substrate bias-voltage generators (for static stores G11C5/146)}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 20/27: {ROM only}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 1/20: Inductors
- H10D 1/47: Resistors having no potential barriers
- H10D 1/68: Capacitors having no potential barriers
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

## Claims

### Claim 1

An electronic element comprising:
a first floating gate device having a first geometry and a first characteristic, the first floating gate device including only a single layer of polysilicon;
a second floating gate device having a second geometry and a second characteristic, wherein the first geometry and the second geometry are the same and the second characteristic is different than the first characteristic and the first characteristic and second characteristic are dependent upon at least parasitic element, the second floating gate device including only a single layer of polysilicon; and
an output, wherein a level of the output is dependent upon the first characteristic and the second characteristic.

### Claim 2 (depends on 1)

The electronic element of claim 1, wherein at least one parasitic element is a parasitic capacitor.

### Claim 3 (depends on 1)

The electronic element of claim 1, wherein at least one parasitic element a parasitic resistor.

### Claim 4 (depends on 1)

The electronic element of claim 1, wherein at least parasitic element is a parasitic inductor.

### Claim 5 (depends on 1)

The electronic element of claim 1, wherein the first device is an active P-channel device.

### Claim 6 (depends on 1)

The electronic element of claim 1, wherein the first device is an active N-channel device.

### Claim 7

An electronic element comprising:
a first floating gate device having a first geometry and a first characteristic, the first floating gate device including only a single layer of polysilicon;
a second floating gate device having a second geometry and a second characteristic, wherein the first geometry and the second geometry are different and the second characteristic is the same as the first characteristic, and the first characteristic and the second characteristic are dependent upon at least one parasitic element, the second floating gate device including only a single layer of polysilicon; and
an output, wherein a level of the output is dependent upon the first characteristic and the second characteristic.

### Claim 8 (depends on 7)

The electronic element of claim 7, wherein at least one parasitic element is a parasitic capacitor.

### Claim 9 (depends on 7)

The electronic element of claim 7, wherein at least one parasitic element a parasitic resistor.

### Claim 10 (depends on 7)

The electronic element of claim 7, wherein at least parasitic element is a parasitic inductor.

### Claim 11 (depends on 7)

The electronic element of claim 7, wherein the first device is an active P-channel device.

### Claim 12 (depends on 7)

The electronic element of claim 7, wherein the first device is an active N-channel device.