# US 9,437,552 B2 · Semiconductor device and method of forming insulating layer around semiconductor die

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- Number: US 9,437,552 B2
- Document ID: US9437552B2
- Status: Granted
- Kind: B2
- Application number: 14/449,869
- Filed: 2014-08-01
- Published: 2014-11-20
- Granted: 2016-09-06
- Earliest claimed: 2010-03-09
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC, Ltd.
- Inventors: Yaojian Lin; Kang Chen; Jianmin Fang; Xia Feng; Xusheng Bao
- Web page: https://patentgrep.com/patent/US9437552B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/40: characterised by their materials
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/01257: {by reflowing}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
depositing an encapsulant between the semiconductor die;
designating a singulation area between the semiconductor die;
forming an insulating layer over the encapsulant in the singulation area;
forming a double channel in the insulating layer in the singulation area while leaving a portion of the encapsulant in the singulation area covered by the insulating layer; and
singulating the semiconductor die through the insulating layer and encapsulant in the singulation area after forming the double channel, the singulation area being devoid of conductive material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the insulating layer reduces outgassing from the encapsulant.

### Claim 3

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
designating a singulation area between the semiconductor die;
forming an insulating layer including a first portion of the insulating layer over the singulation area and a second portion of the insulating layer between a first semiconductor die of the plurality of semiconductor die and a substrate edge;
forming an opening in the first portion of the insulating layer while retaining a part of the first portion of the insulating layer over the singulation area;
singulating the semiconductor die through the second portion of the insulating layer; and
singulating the semiconductor die through the first portion of the insulating layer after forming the opening, the singulation area being devoid of conductive material.

### Claim 4 (depends on 3)

The method of claim 3, further including depositing an encapsulant between the semiconductor die.

### Claim 5 (depends on 3)

The method of claim 3, further including forming a channel in the insulating layer around the semiconductor die.

### Claim 6 (depends on 3)

The method of claim 3, further including forming a double channel in the insulating layer around the semiconductor die.

### Claim 7 (depends on 3)

The method of claim 3, further including forming a net pattern in the insulating layer around the semiconductor die.

### Claim 8 (depends on 3)

The method of claim 3, further including forming a rectangular waveform pattern in the insulating layer around the semiconductor die.

### Claim 9

A semiconductor device, comprising:
a plurality of semiconductor die;
an encapsulant deposited between the semiconductor die including a portion of the encapsulant designated as a saw street, the saw street devoid of conductive material; and
an insulating layer formed over a first portion of the saw street with a second portion of the saw street devoid of the insulating layer, the insulating layer including a rectangular waveform pattern around the semiconductor die.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further including a channel in the insulating layer around the semiconductor die.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further including a double channel in the insulating layer around the semiconductor die.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further including a net pattern in the insulating layer around the semiconductor die.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the insulating layer reduces outgassing from a molding area of the encapsulant.

### Claim 14

A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around the semiconductor die including a portion of the encapsulant designated as a saw street, the saw street devoid of conductive material; and
an insulating layer formed over a first portion of the saw street with a second portion of the saw street devoid of the insulating layer, the insulating layer including a double channel around the semiconductor die.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further including a net pattern in the insulating layer around the semiconductor die.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including a rectangular waveform pattern in the insulating layer around the semiconductor die.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further including an opening formed in the insulating layer over the saw street.