# US 9,437,551 B2 · Concentric bump design for the alignment in die stacking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,551 B2 - Document ID: US9437551B2 - Status: Granted - Kind: B2 - Application number: 14/179,854 - Filed: 2014-02-13 - Published: 2015-08-13 - Granted: 2016-09-06 - Earliest claimed: 2014-02-13 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jung Wei Cheng; Tsung-Ding Wang; Chien-Hsun Lee - Web page: https://patentgrep.com/patent/US9437551B2 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 90/00: Package configurations - H10W 46/101: {characterised by the type of information, e.g. logos or symbols} - H10W 46/301: {for alignment} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01255: {by using masks} - H10W 72/01257: {by reflowing} - H10W 72/019: {of bond pads} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01953: {by etching} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07202: {using auxiliary members} - H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07236: {Soldering or alloying} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07253: {changes in shapes} - H10W 72/221: {Structures or relative sizes} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating} - H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/931: {Shapes of bond pads} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/936: {Multiple bond pads having different shapes} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 72/981: {Auxiliary members, e.g. spacers} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other. ## Claims ### Claim 1 An integrated circuit structure comprising: an alignment bump comprising: a first non-solder metallic bump forming a ring encircling an opening therein, wherein the alignment bump is a dummy bump; a dielectric layer having a top surface in contact with a bottom surface of the first non-solder metallic bump, wherein the dielectric layer extends directly underlying the opening; and an active electrical connector comprising: a second non-solder metallic bump, wherein a top surface of the first non-solder metallic bump and a top surface of the second non-solder metallic bump are substantially coplanar with each other, wherein the active electrical connector is electrically coupled to an active device. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1: wherein the alignment bump further comprises: a first solder layer overlapping and contacting the first non-solder metallic bump, wherein the first solder layer forms a ring encircling the opening therein; and wherein the active electrical connector further comprises: a second solder layer over and contacting the second non-solder metallic bump. ### Claim 3 (depends on 1) The integrated circuit structure of claim 1 further comprising a first package component, with the first package component comprising the alignment bump and the active electrical connector, and wherein the integrated circuit structure further comprises: a second package component over the first package component; and a solder region bonding the first non-solder metallic bump to the second package component. ### Claim 4 (depends on 3) The integrated circuit structure of claim 3, wherein the solder region comprises: a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the solder region; and a top portion over the void, wherein the top portion is connected to the ring portion. ### Claim 5 (depends on 3) The integrated circuit structure of claim 3, wherein a portion of the solder region that overlaps the opening has a bottom surface substantially level with a top surface of the first non-solder metallic bump. ### Claim 6 (depends on 3) The integrated circuit structure of claim 3, wherein a portion of the solder region extends into the opening, and wherein a bottom surface of the solder region that is exposed to the opening has a rounded bottom surface. ### Claim 7 (depends on 1) The integrated circuit structure of claim 1, wherein the alignment bump is cylindrical and is hollow inside. ### Claim 8 An integrated circuit structure comprising: a first package component comprising: an alignment bump at a surface of the first package component, wherein the alignment bump is electrically floating, wherein the alignment bump forms a ring encircling an opening therein, and wherein the alignment bump comprises: a first non-solder metallic bump; a first electrical connector, wherein the first electrical connector has a solid shape with no opening therein, and wherein the first electrical connector comprises: a second non-solder metallic bump; a first solder region contacting the first non-solder metallic bump; a second solder region contacting the second non-solder metallic bump; and a second package component comprising: a second electrical connector bonded to the first electrical connector through the first solder region; and a metal bump bonded to the alignment bump through the second solder region. ### Claim 9 (depends on 8) The integrated circuit structure of claim 8 further comprising: a first Post-Passivation Interconnect (PPI) pad in the first package component, wherein the first PPI pad is in contact with the first electrical connector; and a second PPI pad in the first package component, wherein the second PPI pad is in contact with the alignment bump, and wherein the second PPI pad is electrically floating. ### Claim 10 (depends on 8) The integrated circuit structure of claim 8, wherein the first package component further comprises two additional alignment bumps identical to the alignment bump, wherein the alignment bump and the two additional alignment bumps are distributed to three corners of the first package component. ### Claim 11 (depends on 10) The integrated circuit structure of claim 10, wherein the alignment bump and the two additional alignment bumps are not aligned to any straight line. ### Claim 12 (depends on 8) The integrated circuit structure of claim 8, wherein the alignment bump comprises an inner sidewall facing the opening, and an outer sidewall opposite to the inner sidewall, and wherein the inner sidewall and the outer sidewall are concentric. ### Claim 13 (depends on 8) The integrated circuit structure of claim 8, wherein the opening extends into the second solder region. ### Claim 14 (depends on 8) The integrated circuit structure of claim 8, wherein the first solder region comprises: a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the first solder region; and a top portion over the void, wherein the top portion is connected to the ring portion. ### Claim 15 An integrated circuit structure comprising: a device die comprising: a first non-solder metallic bump forming a full ring, with an opening encircled by the full ring; and a first solder region over the first non-solder metallic bump, wherein the first solder region contacts a top surface of the first non-solder metallic bump, and portions of the top surface of the first non-solder metallic bump in contact with the first solder region forms a full ring, and wherein the first solder region comprises: a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the first solder region; and a top portion over the void, wherein the top portion is connected to the ring portion. ### Claim 16 (depends on 15) The integrated circuit structure of claim 15, wherein the first non-solder metallic bump is at a corner of the device die. ### Claim 17 (depends on 15) The integrated circuit structure of claim 15, wherein the first solder region comprises a portion directly over and sealing the opening. ### Claim 18 (depends on 15) The integrated circuit structure of claim 15 further comprising a second non-solder metallic bump, with no opening encircled by the second non-solder metallic bump, wherein a top surface of the first non-solder metallic bump and a top surface of the second non-solder metallic bump are substantially coplanar with each other. ### Claim 19 (depends on 15) The integrated circuit structure of claim 15, wherein the first non-solder metallic bump is not electrically coupled to any underlying conductive feature. ### Claim 20 (depends on 15) The integrated circuit structure of claim 15 further comprising a package component over and bonded to the device die, wherein the package component comprises a conductive feature bonded to the first non-solder metallic bump through the first solder region.