# US 9,437,548 B2 · Chip package and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,548 B2 - Document ID: US9437548B2 - Status: Granted - Kind: B2 - Application number: 14/740,281 - Filed: 2015-06-16 - Published: 2015-10-01 - Granted: 2016-09-06 - Earliest claimed: 2013-03-14 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Henrik Ewe; Anton Prueckl; Joachim Mahler; Frank Daeche; Josef Hoeglauer; Riccardo Pittassi - Web page: https://patentgrep.com/patent/US9437548B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/453: {comprising flexible metallic tapes} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/467: {Multilayered additional interconnections} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/811: {Multiple chips on leadframes} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip. ## Claims ### Claim 1 A chip package comprising: a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; a first redistribution layer disposed over the at least one chip over a side of the at least one chip facing away from the metallic chip carrier; a second redistribution layer disposed over the at least one chip over the side of the at least one chip facing away from the metallic chip carrier and disposed over the first redistribution layer; and at least one contact hole extending through the encapsulation material to electrically couple the at least one chip with the first redistribution layer and/or the second redistribution layer; wherein the second redistribution layer comprises a surface facing away from the at least one chip that is at least partially exposed. ### Claim 2 (depends on 1) The chip package of claim 1, further comprising: an electrically conductive layer disposed over the metallic chip carrier opposite the first and second redistribution layers. ### Claim 3 (depends on 1) The chip package of claim 1, further comprising: a further metallic chip carrier encapsulated by the encapsulating material. ### Claim 4 (depends on 3) The chip package of claim 3, further comprising: at least one further chip carried by the further metallic chip carrier; wherein the first and/or the second redistribution layer is electrically coupled to the at least one further chip. ### Claim 5 (depends on 1) The chip package of claim 1, wherein the at least one chip comprises at least a first contact on a first chip side and a second contact on a second chip side opposite the first chip side. ### Claim 6 (depends on 5) The chip package of claim 5, wherein the first contact is electrically coupled to the metallic carrier; and wherein the second contact is electrically coupled to the first and/or the second redistribution layer. ### Claim 7 (depends on 6) The chip package of claim 6, wherein the at least one chip comprises a field effect transistor; wherein the first contact is a drain contact; wherein the second contact is a gate contact; and wherein the at least one chip further comprises a source contact. ### Claim 8 (depends on 6) The chip package of claim 6, wherein the at least one chip comprises a bipolar transistor; wherein the first contact is a collector contact; wherein the second contact is a base contact; and wherein the at least one chip further comprises a emitter contact. ### Claim 9 (depends on 1) The chip package of claim 1, wherein the at least one chip comprises a power chip, and wherein the power chip comprises a power chip selected from a group consisting of: a power diode; and a power transistor. ### Claim 10 (depends on 4) The chip package of claim 4, wherein the at least one further chip comprises a further power chip. ### Claim 11 (depends on 10) The chip package of claim 10, wherein the further power chip comprises a power chip selected from a group consisting of: a power diode; and a power transistor. ### Claim 12 (depends on 1) The chip package of claim 1, further comprising: at least one further contact hole extending through the encapsulation material to electrically couple the first redistribution layer to the second redistribution layer. ### Claim 13 (depends on 2) The chip package of claim 2, wherein the electrically conductive layer comprises at least one of a metal, a metal alloy and an electrically conductive adhesive. ### Claim 14 (depends on 2) The chip package of claim 2, wherein the electrically conductive layer has a layer thickness in the range from about 1 μm to about 50 μm. ### Claim 15 (depends on 2) The chip package of claim 2, wherein the electrically conductive layer is patterned. ### Claim 16 (depends on 4) The chip package of claim 4, further comprising wherein the at least one chip and the at least one further chip are connected with each other in a bridge circuit structure. ### Claim 17 A chip package comprising: a first metallic chip carrier and a second metallic chip carrier; at least one chip carried by the first metallic chip carrier; a first redistribution layer disposed over the at least one chip over a side of the at least one chip facing away from the first metallic chip carrier; a second redistribution layer disposed over the at least one chip over the side of the at least one chip facing away from the metallic chip carrier and disposed over the first redistribution layer, wherein a surface of the package facing away from the chip comprises one or more unexposed portions of the second redistribution layer for electrical coupling with external components; encapsulation material encapsulating the at least one chip, the first metallic chip carrier, the second metallic chip carrier, the first redistribution layer and partially encapsulating the second redistribution layer; and at least one contact hole extending through the encapsulation material to electrically couple the at least one chip with the first redistribution layer and/or the second redistribution layer. ### Claim 18 A modular chip package comprising: a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip earner; a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip; and an electrically conductive layer disposed over the metallic chip carrier opposite the plurality of redistribution layers; and at least one electrical component disposed over the electrically conductive layer opposite the plurality of redistribution layers. ### Claim 19 A chip package comprising: a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip earner; a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip; and an electrically conductive layer disposed over the metallic chip carrier opposite the plurality of redistribution layers; and at least one electrical component disposed over the electrically conductive layer opposite the plurality of redistribution layers. ### Claim 20 (depends on 19) The chip package of claim 19, wherein the electrical component comprises a passive element.