# US 9,437,547 B2 · Through silicon vias

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- Number: US 9,437,547 B2
- Document ID: US9437547B2
- Status: Granted
- Kind: B2
- Application number: 15/063,526
- Filed: 2016-03-08
- Published: 2016-06-30
- Granted: 2016-09-06
- Earliest claimed: 2013-03-15
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Benfu Lin; Hong Yu; Lup San Leong; Alex See; Wei Lu
- Web page: https://patentgrep.com/patent/US9437547B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/43: Layouts of interconnections
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

## Claims

### Claim 1

A device comprising:
a substrate with top and bottom surfaces;
a through silicon via (TSV) in the substrate, the TSV extends through top and bottom surfaces of the substrate;
an insulation stack disposed in the TSV, the insulation stack lines the sidewalls of the TSV and comprises a first insulation layer, a polish stop layer and a second insulation layer, wherein the polish stop layer lines the first insulation layer and the second insulation layer lines the polish stop layer in the TSV, the first insulation layer and the polish stop layer further extends over the top surface of the substrate and continuously line the top surface, wherein the polish stop layer is disposed over the first insulation layer; and
a conductive plug disposed in the TSV and fills the TSV having the insulation stack lining the sidewall, wherein a top surface of the conductive plug in the TSV is coplanar with a top surface of the polish stop layer over the top surface of the substrate, the polish stop layer serves as a polish stop for a planarizing process.

### Claim 2 (depends on 1)

The device of claim 1 wherein a bottom surface of the conductive plug is coplanar with the bottom surface of the substrate.

### Claim 3 (depends on 2)

The device of claim 2 wherein the first and second insulation layers comprise silicon oxide and the polish stop layer comprises silicon nitride.

### Claim 4 (depends on 1)

The device of claim 1 wherein the substrate includes a device layer disposed on the top surface of the substrate, the device layer is patterned with an opening corresponding to the TSV, wherein the first insulation layer and the polish stop layer line the device layer over the top surface of the substrate.

### Claim 5 (depends on 4)

The device of claim 4 wherein the device layer comprises an interlevel dielectric (ILD) layer.

### Claim 6 (depends on 4)

The device of claim 4 wherein the device layer comprises a top layer of the device.

### Claim 7 (depends on 6)

The device of claim 6 comprising an interposer layer for connecting the TSV to a contact pad of the device.

### Claim 8 (depends on 4)

The device of claim 4 wherein the first and second insulation layers comprise silicon oxide and the polish stop layer comprises silicon nitride.

### Claim 9 (depends on 1)

The device of claim 1 further comprising a TSV barrier layer disposed in between the insulation stack and the conductive plug in the TSV.

### Claim 10 (depends on 1)

The device of claim 1 wherein the first and second insulation layers comprise silicon oxide and the polish stop layer comprises silicon nitride.

### Claim 11

A device comprising:
a substrate with top and bottom surfaces;
a through silicon via (TSV) in the substrate, the TSV extends from the top surface into the substrate;
an insulation stack disposed in the TSV, the insulation stack lines the sidewalls of the TSV and comprises a first oxide layer, a nitride layer and a second oxide layer, wherein the nitride layer lines the first oxide layer and the second oxide layer lines the nitride layer in the TSV, the first oxide layer and the nitride layer further extends over the top surface of the substrate and continuously line the top surface, wherein the nitride layer is disposed over the first oxide layer; and
a conductive plug disposed in the TSV and fills the TSV having the insulation stack which lines the sidewall of the TSV, wherein a top surface of the conductive plug in the TSV is coplanar with a top surface of the nitride layer over the top surface of the substrate.

### Claim 12 (depends on 11)

The device of claim 11 wherein a bottom surface of the conductive plug is coplanar with the bottom surface of the substrate.

### Claim 13 (depends on 11)

The device of claim 11 wherein the conductive plug extends partially into the substrate.

### Claim 14 (depends on 13)

The device of claim 13 wherein the first and second oxide layers comprises silicon oxide and the nitride layer comprises silicon nitride.

### Claim 15 (depends on 11)

The device of claim 11 further comprising a TSV barrier layer disposed in between the insulation stack and the conductive plug in the TSV.

### Claim 16 (depends on 11)

The device of claim 11 wherein the substrate includes a device layer disposed on the top surface of the substrate, the device layer is patterned with an opening corresponding to the TSV, wherein the first oxide layer and the nitride layer line the device layer over the top surface of the substrate.

### Claim 17 (depends on 16)

The device of claim 16 wherein the device layer comprises an interlevel dielectric (ILD) layer.

### Claim 18 (depends on 17)

The device of claim 17 wherein the first and second oxide layers comprises silicon oxide and the nitride layer comprises silicon nitride.

### Claim 19 (depends on 16)

The device of claim 16 comprising an interposer layer for connecting the TSV to a contact pad of the device.

### Claim 20 (depends on 11)

The device of claim 11 wherein the first and second oxide layers comprise silicon oxide and the nitride layer comprises silicon nitride.