# US 9,437,546 B2 · Method of forming stacked trench contacts and structures formed thereby

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,546 B2
- Document ID: US9437546B2
- Status: Granted
- Kind: B2
- Application number: 14/994,109
- Filed: 2016-01-12
- Published: 2016-05-05
- Granted: 2016-09-06
- Earliest claimed: 2008-06-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bernhard Sell; Oleg Golonzka
- Web page: https://patentgrep.com/patent/US9437546B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

## Claims

### Claim 1

A device structure comprising:
a first gate structure on a substrate, the first gate structure comprising a first gate electrode layer;
a second gate structure on the substrate, the second gate structure comprising a second gate electrode layer;
a source /drain region in the substrate between a first side of the first side of the first gate structure and a second side of the second gate structure;
a first spacer on the first side of the first gate structure and directly adjacent to the first side of the first gate structure;
a second spacer on the second side of the second gate structure and directly adjacent to the second side of the second gate structure;
a nitride etch stop layer directly adjacent to the second spacer;
an interlayer dielectric directly adjacent to the nitride etch stop layer directly adjacent to the second spacer; and
a first contact metal coupled to the source/drain region and in direct contact with the first spacer on the first side of first gate structure and in direct contact with the interlayer dielectric directly adjacent to the nitride etch stop layer directly adjacent to second spacer directly adjacent to the second side of the second gate structure.

### Claim 2 (depends on 1)

The device structure of claim 1 wherein the first gate structure, the second gate structure, the first spacer, the second spacer, the nitride etch stop layer, and the interlayer dielectric each have a planarized top surface which are substantially coplanar with one another.

### Claim 3 (depends on 2)

The device structure of claim 2 further comprising a gate etch stop layer disposed on the planarize surface of each of the first gate structure, the second gate structure, the first spacer, the second spacer, the nitride etch stop layer, and the interlayer dielectric.

### Claim 4 (depends on 3)

The device structure of claim 3 further comprising a second interlayer dielectric disposed on the gate etch stop layer.

### Claim 5 (depends on 4)

The device structure of claim 4 further comprising a second contact metal within the second interlayer dielectric and the gate etch stop layer wherein the second contact metal is directly coupled to the first contact metal, wherein the second contact metal comprises a tapered structure having a bottom portion that is smaller in width than a top portion of the second contact metal.

### Claim 6 (depends on 1)

The device structure of claim 1 wherein the first contact metal is non-tapered contact metal.

### Claim 7 (depends on 1)

The device structure of claim 1 further comprising a silicide on the source/drain region wherein the silicide is closer to the first side of the first gate structure than to the second side of the second gate structure.

### Claim 8

A method of forming a device comprising:
forming a first gate structure comprising a first gate electrode layer and a second gate structure comprising a second gate electrode layer on a substrate;
forming a source/drain region in the substrate between a first side of a first gate structure and a second side of the second gate structure;
forming a first spacer on the first side of the first gate structure and directly adjacent to the first side of the first gate structure and a second spacer on the second side of the second gate structure and directly adjacent to the second side of the second gate structure;
forming a nitride etch stop layer directly adjacent to the second spacer;
forming an interlayer dielectric directly adjacent to the nitride etch stop layer directly adjacent to the second spacer; and
forming a first contact metal coupled to the source/drain region and in direct contact with the first spacer on the first side of the first gate structure and in direct contact with the interlayer dielectric directly adjacent to nitride etch stop layer directly adjacent to the second spacer on the second side of the second gate structure.

### Claim 9 (depends on 8)

The method of claim 8 further comprising planarizing the first gate structure, the second gate structure, the first spacer, the second spacer, the nitride etch stop layer and the interlayer dielectric to create a planarized top surface for each of the first gate structure, the second gate structure, the first spacer, the second spacer, the nitride etch stop layer and the interlayer dielectric such which are all substantially coplanar with one another.

### Claim 10 (depends on 9)

The method of claim 9 further comprising forming a gate etch stop layer on the planarized surface of each of the first gate structure, the second gate structure, the first spacer, the second spacer, the nitride etch stop layer, and the interlayer dielectric.

### Claim 11 (depends on 10)

The method of claim 10 further comprising forming a second interlayer dielectric on the gate etch stop layer.

### Claim 12 (depends on 11)

The method of claim 11 further comprising forming a second contact metal within the second interlayer dielectric that is directly coupled to the first contact metal wherein the second contact metal comprises a tapered structure having a bottom portion that is smaller in width than a top portion of the second contact metal.

### Claim 13 (depends on 8)

The method of claim 8 wherein the contact metal is a non-tapered contact metal.

### Claim 14 (depends on 8)

The method of claim 8 further comprising forming a silicide on the source/drain wherein the silicide is closer to the first side of the first gate structure than to the second side of the second gate structure.