# US 9,437,544 B2 · Semiconductor device

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- Number: US 9,437,544 B2
- Document ID: US9437544B2
- Status: Granted
- Kind: B2
- Application number: 14/690,982
- Filed: 2015-04-20
- Published: 2015-08-13
- Granted: 2016-09-06
- Earliest claimed: 2007-11-16
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Katsumi Sameshima
- Web page: https://patentgrep.com/patent/US9437544B2

## CPC

- H10W 72/90: Bond pads, in general
- H10W 20/43: Layouts of interconnections
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/07355: {changes in materials}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/231: {Shapes}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor chip, a wiring on the chip, an insulating film coating the wiring and having an opening partially exposing the wiring, a Ti/W film on a portion of the wiring facing the opening, a Cu layer on the Ti/W film and the wiring's exposed portion, and having a peripheral edge protruding away from the opening more than Ti/W film's peripheral edge in parallel to an insulating film surface, and a solder ball bonded to the Cu layer. The protrusion of the Cu layer's peripheral edge with respect to the Ti/W film's peripheral edge is greater than the Ti/W film's thickness. The Ti/W film's surface doesn't vertically surpass the Cu layer's upper surface in the opening's center. A Cu layer/solder ball interface is arc-shaped on both sides of the Cu layer's upper surface in a cross section taken perpendicularly to the Cu layer's upper surface.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip;
a wiring formed on the semiconductor chip;
an insulating film, coating the wiring and having an opening for partially exposing the wiring from the insulating film;
a first film made of Ti and W, formed on a portion of the wiring facing the opening;
a Cu layer, formed by plating on the first film and on a portion of the wiring exposed through the insulating film such that an upper surface of the Cu layer is a uniform distance from an upper surface of the wiring, and having a peripheral edge portion thereof protruding away from the opening more than a peripheral edge of the first film in a direction parallel to a surface of the insulating film; and
a solder ball bonded to the Cu layer,
wherein a distance between the surface of the insulating film and the Cu layer is fixed,
a protrusion amount of the peripheral edge portion of the Cu layer with respect to the peripheral edge of the first film is greater than a thickness of the first film,
the Cu layer is stacked high enough that a surface of the first film does not vertically surpass the upper surface of the Cu layer in the center of the opening, and
an interface between the Cu layer and the solder ball is arc-shaped on both sides of the upper surface of the Cu layer in a cross section taken perpendicularly to the upper surface of the Cu layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a peripheral edge portion of the first film is formed to ride on a circumference of the opening in the insulating film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the Cu layer and the first film are both disposed over all surfaces of the opening.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first film is disposed over all surfaces of the opening.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the surface of the insulating film is separated from the peripheral edge portion of the Cu layer by a gap.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the thickness of the first film is around 180 nm.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the solder ball partly covers the Cu layer such that a portion of a surface of the Cu layer is exposed form the solder ball.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the portion of the surface of the Cu layer exposed from the solder ball includes a surface of the peripheral edge portion of the Cu layer that faces the surface of the insulating film via a gap therebetween.

### Claim 9

A semiconductor device comprising:
a semiconductor chip;
a wiring on the semiconductor chip;
a passivation film, coating the wiring and having an opening for partially exposing the wiring from the passivation film;
a barrier film on a portion of the wiring facing the opening and having a peripheral edge;
a post bump formed by plating on the barrier film such that the post bump has a uniform thickness, and having a peripheral edge portion protruding away from the opening, a protrusion amount of the peripheral edge portion of the post bump with respect to the peripheral edge of the barrier film being greater than a thickness of the barrier film; and
a solder ball bonded to the post bump.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein a peripheral edge portion of the barrier film is formed to ride on a circumference of the opening in the passivation film.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein the post bump and the barrier film are both disposed over all surfaces of the opening.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein the barrier film is disposed over all surfaces of the opening.

### Claim 13 (depends on 9)

The semiconductor device according to claim 9, wherein the surface of the passivation film is separated from the peripheral edge portion of the post bump by a gap.

### Claim 14 (depends on 9)

The semiconductor device according to claim 9, wherein the thickness of the barrier film is around 180 nm.

### Claim 15 (depends on 9)

The semiconductor device according to claim 9, wherein the solder ball partly covers the post bump such that a portion of a surface of the post bump is exposed form the solder ball.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the portion of the surface of the post bump exposed from the solder ball includes a surface of the peripheral edge portion of the post bump that faces the surface of the passivation film via a gap therebetween.

### Claim 17 (depends on 9)

The semiconductor device according to claim 9, wherein the barrier film is made TiW, and the post bump is made of Cu.