# US 9,437,542 B2 · Chip package structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,542 B2 - Document ID: US9437542B2 - Status: Granted - Kind: B2 - Application number: 14/985,423 - Filed: 2015-12-31 - Published: 2016-04-21 - Granted: 2016-09-06 - Earliest claimed: 2014-07-07 - Assignees: ChipMOS Technologies Inc. - Applicants: ChipMOS Technologies Inc. - Inventors: Tsung-Jen Liao - Web page: https://patentgrep.com/patent/US9437542B2 ## CPC - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/778: {in encapsulations} - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/685: comprising multiple insulating layers - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9413: {on encapsulations} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip. ## Claims ### Claim 1 A chip package structure, comprising: a chip, comprising an active surface and a back surface opposite to the active surface; a plurality of heat dissipating pillars, disposed around a periphery region of the chip; a molding compound, covering the chip and the periphery region and exposing the active surface, wherein the heat dissipating pillars are disposed at the molding compound, and the molding compound exposes a part of each of the heat dissipating pillars, the molding compound comprises an upper surface, a lower surface opposite to the upper surface, and a plurality of openings, the lower surface is substantially aligned with respect to the active surface, the openings are located on the upper surface, the heat dissipating pillars are embedded into the molding compound, a surface of each of the heat dissipating pillar away from the upper surface is projected from the lower surface, and each of the openings exposes a top surface of a corresponding one of the heat dissipating pillars; and a redistribution circuit layer, covering the active surface and the lower surface of the molding compound, and the redistribution circuit layer being electrically connected with the chip. ### Claim 2 (depends on 1) The chip package structure as claimed in claim 1, wherein the redistribution circuit layer covers the surface of each of the heat dissipating pillar away from the upper surface. ### Claim 3 (depends on 1) The chip package structure as claimed in claim 1, wherein the molding compound comprises an upper surface and a lower surface opposite to the upper surface, the lower surface is substantially aligned with respect to the active surface, the heat dissipating pillars are embedded into the molding compound, and surfaces of the heat dissipating pillars away from the lower surface are aligned with respect to the upper surface to be exposed by the molding compound. ### Claim 4 (depends on 1) The chip package structure as claimed in claim 1, wherein the redistribution circuit layer comprises a first protective layer, a patterned conductive layer, a second protective layer, and a plurality of solder pads. ### Claim 5 (depends on 4) The chip package structure as claimed in claim 4, wherein the first protective layer covers the active surface and the lower surface of the molding compound, the patterned conductive layer is disposed at the first protective layer and electrically connected to the chip, the solder pads are disposed on the first protective layer and electrically connected to the patterned conductive layer, and the second protective layer is disposed on the first protective layer and exposes the solder pads. ### Claim 6 (depends on 4) The chip package structure as claimed in claim 4, further comprising a plurality of solder balls respectively disposed on the solder pads. ### Claim 7 A chip package structure, comprising: a chip, comprising an active surface and a back surface opposite to the active surface; at least one inducting coil, disposed around a first periphery region of the chip; a plurality of heat dissipating pillars, disposed around a second periphery region of the chip, wherein the first and second periphery regions are not overlapped with each other; a molding compound, covering the chip, the first periphery region, and the second periphery region, and the molding compound exposing the active surface, wherein the inducting coil and the heat dissipating pillars are disposed on the molding compound, and the molding compound exposes a part of each of the heat dissipating pillars; and a redistribution circuit layer, covering the active surface and a part of the molding compound, and the redistribution circuit layer being electrically connected with the chip. ### Claim 8 (depends on 7) The chip package structure as claimed in claim 7, wherein the chip further comprises a plurality of pads disposed on the active surface, and the redistribution circuit layer electrically connects the inducting coil to one of the pads. ### Claim 9 (depends on 8) The chip package structure as claimed in claim 8, wherein the redistribution circuit layer comprises a patterned conductive layer that connects a part of the inducting coil projected from the lower surface to one of the pads. ### Claim 10 (depends on 8) The chip package structure as claimed in claim 8, wherein the molding compound further comprises a via that exposes a part of the inducting coil, the redistribution circuit layer comprises a patterned conductive layer, and the patterned conductive layer connects the part exposed by the via to one of the pads. ### Claim 11 (depends on 10) The chip package structure as claimed in claim 10, wherein the via is disposed at the lower surface of the molding compound. ### Claim 12 (depends on 7) The chip package structure as claimed in claim 7, wherein the molding compound comprises an upper surface, a lower surface opposite to the upper surface, and a plurality of openings, the lower surface is substantially aligned with respect to the active surface, the inducting coil and the heat dissipating pillars are embedded into the molding compound, surfaces of the inducting coil and the heat dissipating pillars away from the upper surface are projected from the lower surface, the openings are located on the upper surface, and each of the openings exposes a top surface of a corresponding one of the heat dissipating pillars. ### Claim 13 (depends on 12) The chip package structure as claimed in claim 12, wherein the redistribution circuit layer covers the surfaces of the inducting coil and the heat dissipating pillars away from the upper surface. ### Claim 14 (depends on 7) The chip package structure as claimed in claim 7, wherein the molding compound comprises an upper surface and a lower surface opposite to the upper surface, the lower surface is substantially aligned with respect to the active surface, the inducting coil and the heat dissipating pillars are embedded into the molding compound, and surfaces of the inducting coil and the heat dissipating pillars are aligned with respect to the upper surface. ### Claim 15 (depends on 7) The chip package structure as claimed in claim 7, wherein the redistribution circuit layer comprises a first protective layer, a patterned conductive layer, a second protective layer, and a plurality of solder pads. ### Claim 16 (depends on 15) The chip package structure as claimed in claim 15, further comprising a plurality of solder balls respectively disposed on the solder pads. ### Claim 17 (depends on 7) The chip package structure as claimed in claim 7, wherein the first protective layer covers the active surface and the lower surface of the molding compound, the patterned conductive layer is disposed at the first protective layer and electrically connects the inducting coil and the chip, the solder pads are disposed on the first protective layer and electrically connected to the patterned conductive layer, and the second protective layer disposed on the first protective layer and exposes the solder pads. ### Claim 18 (depends on 7) The chip package structure as claimed in claim 7, wherein the first periphery region and second periphery region surround the chip together.