# US 9,437,541 B2 · Patterning approach to reduce via to via minimum spacing

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- Number: US 9,437,541 B2
- Document ID: US9437541B2
- Status: Granted
- Kind: B2
- Application number: 14/724,718
- Filed: 2015-05-28
- Published: 2015-09-17
- Granted: 2016-09-06
- Earliest claimed: 2013-03-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Yuan Ting; Chung-Wen Wu
- Web page: https://patentgrep.com/patent/US9437541B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a first mask layer over an underlying layer;
forming a first line opening in the first mask layer using a first patterning process;
after forming the first line opening, forming a second line opening in the first mask layer using a second patterning process;
forming a second mask layer over the first mask layer, the second mask layer having a via opening, the via opening exposing portions of the first line opening and the second line opening;
etching vias in the underlying layer using the first mask layer and the second mask layer as mask;
removing the second mask layer; and
after removing the second mask layer, simultaneously etching to extend the vias and to form lines in the underlying layer using the first mask layer as a mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein a distance between the first line opening and the second line opening is less than a minimal spacing allowed by a single patterning step.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second mask layer comprises a photoresist.

### Claim 4 (depends on 1)

The method of claim 1, further comprising removing the first mask layer and filling the vias and lines with a conductive material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the underlying layer comprises an etch stop layer over a dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the forming the first line opening and the forming the second line opening exposes the etch stop layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the etching vias comprises etching vias through the etch stop layer and into the dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein top views of the vias have a trapezoid geometry.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming a first layer over a substrate;
forming a second layer over the first layer;
patterning the second layer to form a first opening, the first opening exposing the first layer;
after patterning the second layer to form the first opening, patterning the second layer to form a second opening, the second opening exposing the first layer;
forming a third layer over the second layer;
patterning the third layer to form a combined opening, the combined opening overlapping portions of the first opening and the second opening, the combined opening exposing the first layer;
etching a first portion of the first layer and the substrate through the combined opening to obtain first recesses extending into the substrate;
removing the third layer; and
after removing the third layer, etching the first layer and the substrate to extend the first opening and the second opening into the substrate and to extend the first recesses in the substrate to forms vias and lines in the substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein a distance between the first opening and the second opening is less than a minimal spacing allowed by a single patterning step.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing the first layer and the second layer and filling the vias and lines in the substrate with a conductive material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the substrate comprises a dielectric layer, the vias and lines being formed in the dielectric layer.

### Claim 13 (depends on 9)

The method of claim 9, wherein top view of the first via has a trapezoid geometry.

### Claim 14 (depends on 9)

The method of claim 9, wherein the third layer comprises a photoresist.

### Claim 15

A device comprising:
a substrate;
a dielectric layer over the substrate;
a first conductive element in the dielectric layer;
a second conductive element in the dielectric layer;
a first via under the first conductive element; and
a second via under the second conductive element;
wherein a first via-to-via distance between the first via and the second via is less than a minimal spacing allowed by a single patterning step.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first conductive element is a first line and the second conductive element is a second line.

### Claim 17 (depends on 16)

The device of claim 16, wherein the first via-to-via distance is equal to a line-to-line distance between the first line and the second line.

### Claim 18 (depends on 15)

The device of claim 15, wherein top views of the first via and the second via have a trapezoid geometry.

### Claim 19 (depends on 15)

The device of claim 15 further comprising:
a third via positioned below a third line in the dielectric layer; and
a fourth via positioned below a fourth line in the dielectric layer,
wherein a via-to-via pitch between the third via and the fourth via is larger than or equal to a minimal spacing allowed by a single patterning step.

### Claim 20 (depends on 15)

The device of claim 15, wherein a distance between the first conductive element and the second conductive element is less than a resolution limit of ultra violet (UV) or extreme UV (EUV).