# US 9,437,539 B2 · Dielectric region in a bulk silicon substrate providing a high-Q passive resonator

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- Number: US 9,437,539 B2
- Document ID: US9437539B2
- Status: Granted
- Kind: B2
- Application number: 14/830,816
- Filed: 2015-08-20
- Published: 2015-12-10
- Granted: 2016-09-06
- Earliest claimed: 2014-03-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: James S. Dunn; Zhong-Xiang He; Qizhi Liu
- Web page: https://patentgrep.com/patent/US9437539B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/68: Capacitors having no potential barriers
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/43: Layouts of interconnections
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10D 1/20: Inductors
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 44/241: {for passive devices or passive elements}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

## Claims

### Claim 1

A mixed-signal integrated circuit (IC), comprising:
a bulk silicon (Si) substrate of a silicon wafer;
a dielectric region extending down into said bulk Si substrate and having vertical sidewalls that are oriented in <100> directions, according to the Miller index;
a hard mask including a plurality of holes oriented in said <100> directions, said hard mask overlying said dielectric region;
a dielectric layer that overlies said hard mask and said dielectric region;
a high-Q passive resonator formed in metallization layers associated with back-end-of-line (BEOL) processes, said high-Q passive resonator overlying said dielectric region; and
a topmost front-end-of-line (FEOL) layer above said dielectric layer and beneath said high-Q passive resonator formed in said metallization layers.

### Claim 2 (depends on 1)

The mixed-signal IC of claim 1, said dielectric region comprising silicon oxide.

### Claim 3 (depends on 1)

The mixed-signal IC of claim 1, said hard mask comprising one of silicon oxide and silicon nitride.

### Claim 4 (depends on 1)

The mixed-signal IC of claim 1, said plurality of holes including any of square holes, rectangular holes, and a combination of square holes and rectangular holes.

### Claim 5 (depends on 1)

The mixed-signal IC of claim 1, said dielectric layer comprising one of a silicon oxide and a silicon nitride.

### Claim 6 (depends on 1)

The mixed-signal IC of claim 1, said high-Q passive resonator comprising one of an inductor and a capacitor.