# US 9,437,538 B2 · Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect

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- Number: US 9,437,538 B2
- Document ID: US9437538B2
- Status: Granted
- Kind: B2
- Application number: 14/292,925
- Filed: 2014-06-01
- Published: 2014-09-18
- Granted: 2016-09-06
- Earliest claimed: 2010-06-24
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC, Ltd.
- Inventors: Reza A. Pagaila; Yaojian Lin; Jun Mo Koo
- Web page: https://patentgrep.com/patent/US9437538B2

## CPC

- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/20: Configurations of stacked chips
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.

## Claims

### Claim 1

A semiconductor device, comprising:
a first semiconductor die including a first sloped side surface extending from an active surface to a back surface, the back surface smaller than the active surface;
a conductive layer contacting the back surface of the first semiconductor die and the first sloped side surface and including a segment comprising a surface coplanar with the active surface of the first semiconductor die;
an encapsulant disposed over the conductive layer and the first sloped side surface of the first semiconductor die, the back surface of the first semiconductor die being devoid of the encapsulant;
a redistribution layer (RDL) formed over the encapsulant and the back surface of the first semiconductor die;
an interconnect structure formed under the surface of the conductive layer that is coplanar with the active surface of the first semiconductor die and electrically connected to the conductive layer; and
a first bump formed under the interconnect structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including:
a second semiconductor die disposed over the back surface of the first semiconductor die; and
a second bump disposed between the conductive layer and the second semiconductor die.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the RDL physically contacts the back surface of the first semiconductor die and the encapsulant.

### Claim 4

A semiconductor device, comprising:
a first semiconductor die including a sloped side surface extending from an active surface to a back surface, the back surface smaller than the active surface;
a conductive layer formed over the back surface and sloped side surface;
an encapsulant disposed over the conductive layer;
a redistribution layer (RDL) formed over the back surface of the first semiconductor die and encapsulant; and
an interconnect structure including an insulating layer formed under the first semiconductor die and encapsulant and electrically connected to the conductive layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further including:
a second semiconductor die disposed over the back surface; and
a bump disposed between the conductive layer and the second semiconductor die.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, further including a shielding layer formed over the back surface.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, further including a heat sink disposed over the back surface.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein the back surface of the first semiconductor die is devoid of the encapsulant.

### Claim 9 (depends on 4)

The semiconductor device of claim 4, wherein the conductive layer physically contacts the back surface of the first semiconductor die.

### Claim 10 (depends on 4)

The semiconductor device of claim 4, wherein the RDL physically contacts the back surface of the first semiconductor die and the encapsulant.

### Claim 11 (depends on 4)

The semiconductor device of claim 4, further including an underfill material disposed under the active surface opposite the back surface of the first semiconductor die.

### Claim 12

A semiconductor device, comprising:
a first semiconductor die including a sloped side surface extending from an active surface to a back surface, the back surface smaller than the active surface;
a conductive layer formed over the sloped side surface and including a first segment that is coplanar with the active surface of the first semiconductor die and a second segment in contact with the back surface of the first semiconductor die;
an encapsulant disposed over the conductive layer;
a redistribution layer (RDL) formed over the encapsulant and the back surface of the first semiconductor die;
a first interconnect structure formed under the first semiconductor die; and
an external connection provided by a second interconnect structure formed under the first interconnect structure.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first interconnect structure is electrically connected to the conductive layer.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further including:
a second semiconductor die disposed over the back surface of the first semiconductor die; and
a bump disposed between the conductive layer and the second semiconductor die.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the active surface of the first semiconductor die is devoid of first segment of the conductive layer.

### Claim 16

A semiconductor device, comprising:
a first semiconductor die including a sloped side surface extending from an active surface to a back surface, the back surface smaller than the active surface;
a conductive layer formed over the back surface and sloped side surface;
an encapsulant disposed over the conductive layer; a redistribution layer (RDL) formed over the back surface of the first semiconductor die and encapsulant; and
an interconnect structure formed under the first semiconductor die including an external connection.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the interconnect structure is electrically connected to the conductive layer.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further including:
a second semiconductor die disposed over the back surface; and
a bump disposed between the conductive layer and the second semiconductor die.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, further including a shielding layer formed over the back surface.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, further including an underfill material disposed under the active surface opposite the back surface of the first semiconductor die.