# US 9,437,536 B1 · Reversed build-up substrate for 2.5D

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- Number: US 9,437,536 B1
- Document ID: US9437536B1
- Status: Granted
- Kind: B1
- Application number: 14/885,466
- Filed: 2015-10-16
- Granted: 2016-09-06
- Earliest claimed: 2015-05-08
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Liang Wang; Rajesh Katkar; Hong Shen; Cyprian Emeka Uzoh; Belgacem Haba
- Web page: https://patentgrep.com/patent/US9437536B1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/01: Manufacture or treatment
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/12: characterised by their shape
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07254: {changes in dispositions}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/951: {Materials of bond pads}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

## Claims

### Claim 1

A method of making an assembly, comprising:
forming a circuit structure defining oppositely-facing front and rear major surfaces, one of the front and rear surfaces being mechanically coupled to a surface of a carrier, the forming of the circuit structure including:
forming a first dielectric layer mechanically coupled to the carrier, the first dielectric layer defining the front surface, the first dielectric layer including front contacts at the front surface configured for joining with corresponding contacts of one or more microelectronic elements, and first conductive traces supported by the first dielectric layer, at least some of the first traces having maximum widths less than five microns, and
forming rear conductive elements at the rear surface electrically coupled with the front contacts through the first traces;
forming a substrate onto the rear surface of the circuit structure, the forming of the substrate including:
forming a dielectric element directly on the rear surface of the circuit structure, the dielectric element having first conductive elements facing the rear conductive elements of the circuit structure and joined thereto, the dielectric element further including second conductive traces supported by the dielectric element and electrically coupled with the first conductive elements, at least some of the second conductive traces having maximum widths greater than five microns, and
forming terminals at a surface of the substrate facing away from the rear conductive elements, the terminals electrically coupled with the second traces.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the dielectric element is a first dielectric element, and forming the substrate further comprises:
forming a substrate core having an upper surface attached to the first dielectric element, a lower surface opposite from the upper surface, and a plurality of electrically conductive interconnects extending therethrough; and
forming a second dielectric element attached to the lower surface of the substrate core, and forming third conductive traces supported by the second dielectric element and electrically coupled with the conductive interconnects, wherein the terminals are formed on or within the second dielectric element and are electrically coupled with the second traces through the conductive interconnects and the third traces.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein at least some of the conductive interconnects have an upper cross section in a plane of the upper surface of the substrate core, and a lower cross section in a plane of the lower surface of the substrate core, and the conductive interconnects are formed after forming the substrate core by a process comprising:
plating an electrically conductive material into open ends of through holes at the lower surface of the substrate core, the through holes extending through the thickness of the substrate core, such that the upper cross section contains a higher amount of the conductive material than the lower cross section.

### Claim 4 (depends on 3)

The method as claimed in claim 3, further comprising, before forming the conductive interconnects, forming at least one of a conductive adhesion layer and a barrier layer extending through the substrate core, the at least one of the conductive adhesion layer and the barrier layer comprising a different material than a bulk conductive material of the conductive interconnects, wherein the conductive interconnects are formed onto a surface of the at least one of the conductive adhesion layer and the barrier layer.

### Claim 5 (depends on 3)

The method as claimed in claim 3, wherein at least some of the conductive interconnects include recesses therein, the method further comprising depositing a dielectric material into the recesses.

### Claim 6 (depends on 1)

The method as claimed in claim 1, further comprising, before forming the substrate, planarizing the first dielectric layer.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the forming of the rear conductive elements includes forming a second dielectric layer mechanically coupled with the first dielectric layer, and forming the rear conductive elements at the second dielectric layer.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein the forming of the rear conductive elements includes forming intermediate conductive traces supported by the second dielectric layer, the rear conductive elements electrically coupled with the first traces through the intermediate traces.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein at least some of the first traces have maximum widths less than two microns.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein at least some of the second traces have maximum widths less than ten microns.

### Claim 11 (depends on 1)

The method as claimed in claim 1, further comprising separating the circuit structure from the carrier.

### Claim 12 (depends on 11)

The method as claimed in claim 11, further comprising, after separating the circuit structure from the carrier, forming electrically conductive bumps at the front surface configured for connection with the contacts of the one or more microelectronic elements, the bumps being formed in contact with the front contacts.

### Claim 13 (depends on 12)

The method as claimed in claim 12, further comprising electrically coupling the one or more microelectronic elements with the bumps, the contacts of the one or more microelectronic elements facing the bumps and joined thereto.

### Claim 14 (depends on 1)

The method as claimed in claim 1, further comprising:
before forming the circuit structure,
forming a sacrificial dielectric layer having a top surface mechanically coupled to the carrier and defining a bottom surface opposite from the top surface,
forming openings at the bottom surface extending into the sacrificial dielectric layer in a direction toward the top surface, and
forming electrically conductive bumps within the openings, the bumps configured for connection with the contacts of the one or more microelectronic elements,
wherein the front surface of the circuit structure is formed on the bottom surface of the sacrificial dielectric layer, and the front contacts of the circuit structure are formed in contact with the bumps; and
after separating the circuit structure from the carrier, removing the sacrificial dielectric layer to expose the bumps at the front surface of the circuit structure.

### Claim 15 (depends on 14)

The method as claimed in claim 14, further comprising electrically coupling the one or more microelectronic elements with the bumps, the contacts of the one or more microelectronic elements facing the bumps and joined thereto.

### Claim 16 (depends on 1)

The method as claimed in claim 1, wherein the substrate has a CTE in a horizontal plane of the substrate, the method further comprising forming a groove within the substrate at least partially extending in a direction transverse to the surface of the substrate, and depositing a material at least partially filling the groove, the material having a CTE in a horizontal plane of the substrate that is lower than the CTE of the substrate.

### Claim 17 (depends on 11)

The method as claimed in claim 11, further comprising, after separating the circuit structure from the carrier:
electrically coupling the one or more microelectronic elements with the front contacts, the contacts of the microelectronic elements facing the front contacts and joined thereto; and
separating the assembly into a first assembly including a first plurality of the microelectronic elements and a second assembly including a second plurality of the microelectronic elements.

### Claim 18

An assembly, comprising:
a circuit structure made of a plurality of dielectric layers and electrically conductive features thereon, the circuit structure having front and rear opposite surfaces and a maximum thickness of less than 30 microns in a direction normal to the front surface,
the electrically conductive features comprising front contacts at the front surface configured for joining with corresponding contacts of one or more microelectronic elements, rear conductive elements at the rear surface, and first conductive traces having maximum widths less than five microns, the front contacts electrically coupled with the rear conductive elements through the first traces; and
a substrate defining a first surface laminated onto the rear surface of the circuit structure and a second surface opposite therefrom, the substrate comprising a dielectric element and having terminals at the second surface, the dielectric element defining the first surface,
the dielectric element having first conductive elements facing the rear conductive elements and joined thereto, and second conductive traces electrically coupled to the first conductive elements and extending in directions parallel to the first surface, at least some of the second traces having maximum widths greater than five microns.

### Claim 19 (depends on 18)

The assembly as claimed in claim 18, wherein the dielectric element is a first dielectric element, the substrate further including:
a substrate core having an upper surface attached to the first dielectric element, a lower surface opposite from the upper surface, and a thickness in a first direction normal to the upper surface, the substrate core having a plurality of electrically conductive interconnects extending in the first direction through a thickness of the substrate core; and
a second dielectric element attached to the lower surface of the substrate core and having third conductive traces electrically coupled with the conductive interconnects, a surface of the second dielectric element defining the second surface of the substrate, wherein the terminals are electrically coupled with said second traces through the conductive interconnects and the third traces.

### Claim 20 (depends on 19)

The assembly as claimed in claim 19, wherein at least some of the conductive interconnects have an upper cross section in a plane of the upper surface of the substrate core and a lower cross section in a plane of the lower surface of the substrate core, and the upper cross section contains a higher amount of conductive material than the lower cross section.

### Claim 21 (depends on 20)

The assembly as claimed in claim 20, wherein the substrate core has at least one of a conductive adhesion layer and a barrier layer extending circumferentially around the conductive interconnects and extending through the substrate core, the at least one of the conductive adhesion layer and the barrier layer comprising a different material than a bulk conductive material of the conductive interconnects.

### Claim 22 (depends on 18)

The assembly as claimed in claim 18, wherein the rear surface of the circuit structure is united with the first surface of the substrate, and the interface between the circuit structure and the substrate is devoid of solder.

### Claim 23 (depends on 18)

A system comprising the assembly as claimed in claim 18 and one or more other electronic components electrically connected with the assembly.

### Claim 24 (depends on 23)

The system as claimed in claim 23, further comprising a housing, the assembly and the one or more other electronic components being assembled with the housing.