# US 9,437,533 B2 · Semiconductor memory system

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- Number: US 9,437,533 B2
- Document ID: US9437533B2
- Status: Granted
- Kind: B2
- Application number: 14/511,676
- Filed: 2014-10-10
- Published: 2015-01-22
- Granted: 2016-09-06
- Earliest claimed: 2011-03-16
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Hayato Masubuchi; Naoki Kimura; Manabu Matsumoto; Toyota Morimoto
- Web page: https://patentgrep.com/patent/US9437533B2

## CPC

- H10W 90/00: Package configurations
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- H05K 1/0225: {Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence)}
- H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion}
- H05K 1/0298: {Multilayer circuits}
- H05K 1/181: associated with surface mounted components
- H05K 3/305: {Affixing by adhesive}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10W 20/427: {Power or ground buses}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H05K 2201/09136: Means for correcting warpage
- H05K 2201/09681: Mesh conductors, e.g. as a ground plane
- H05K 2201/10159: Memory
- H10W 74/114: {by a substrate and the encapsulations}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10B: ELECTRONIC MEMORY DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories on the substrate, wherein
the substrate includes:
a first metal layer having a first pattern density, the first metal layer being electrically connected to the nonvolatile semiconductor memories and being located on a first side of the substrate;
a second metal layer having a second pattern density, the second metal layer being located on a second side of the substrate;
a plurality of third metal layers disposed between the first and second metal layers and having respective third pattern densities; and
insulating layers provided between the first metal layer and a first one of the third metal layers adjacent to the first metal layer, between the second metal layer and a second one of the third metal layers adjacent to the second metal layer, and between adjacent ones of the third metal layers, wherein
a first group of metal layers includes n metal layers including the first metal layer and (n−1) adjacent third metal layers, a second group of n metal layers includes the second metal layer and (n−1) adjacent third metal layers different from the (n−1) third metal layers in the first group, a first density obtained from the first and third pattern densities of the first group of metal layers is equal to or greater than a second density obtained from the second and third pattern densities of the second group of metal layers, and a difference between the first density and the second density is 7.5% or less.

### Claim 2 (depends on 1)

The device according to claim 1, wherein:
the first density comprises an average of the first pattern density and the third pattern densities of the third layers in the first group of metal layers; and
the second density comprises an average of the second pattern density and the third pattern densities of the third layers in the second group of metal layers.

### Claim 3 (depends on 1)

The device according to claim 1, wherein at least one of the third metal layers comprises a shield layer.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the second metal layer is a mesh layer.

### Claim 5 (depends on 4)

The device according to claim 4, wherein a pattern density of the mesh layer is selected to achieve said difference of 7.5% or less.

### Claim 6 (depends on 1)

The device according to claim 1, wherein a pattern density of the second layer is selected to achieve said difference of 7.5% or less.

### Claim 7 (depends on 1)

The device according to claim 1, wherein
the first metal layer is a signal layer;
a first one of the third metal layers in the first group of metal layers is a plane layer;
third metal layers in the first group of metal layers other than the first one of the third metal layers are signal layers;
the second metal layer is a mesh layer;
a second one of the third metal layers in the second group is a signal layer; and
third metal layers in the second group of metal layers other than the second one of the third metal layers are plane layers.

### Claim 8 (depends on 1)

The device according to claim 1, wherein
at least one of the third metal layers in the first group of metal layers comprises a plane layer; and
at least one of the third metal layers in the second group of metal layers comprises a signal layer.

### Claim 9 (depends on 1)

The device according to claim 1, wherein the device consists of 2n layers.

### Claim 10 (depends on 1)

The device according to claim 1, wherein the first density is about 60% and the second density is about 60-67.5%.

### Claim 11 (depends on 1)

The device according to claim 1, comprising slits formed in one of the layers in the second group of metal layers.

### Claim 12

A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories on the substrate, wherein
the substrate includes:
a first metal layer having a first pattern density, the first metal layer being electrically connected to the nonvolatile semiconductor memories and being located on a first side of the substrate;
a second metal layer having a second pattern density;
a plurality of third metal layers disposed between the first and second metal layers and having respective third pattern densities;
a shield layer disposed on a second side of the substrate; and
insulating layers provided between the first metal layer and a first one of the third metal layers adjacent to the first metal layer, between the second metal layer and a second one of the third metal layers adjacent to the second metal layer, between adjacent ones of the third metal layers, and between the second metal layer and the shield layer, wherein a first group of metal layers includes n metal layers including the first metal layer and (n−1) adjacent third metal layers, a second group of n metal layers includes the second metal layer and (n−1) adjacent third metal layers different from the (n−1) third metal layers in the first group, a first density obtained from the first and third pattern densities of the first group of metal layers is equal to or greater than a second density obtained from the second and third pattern densities of the second group of metal layers, and a difference between the first density and the second density is 7.5% or less.

### Claim 13

A wiring substrate, comprising:
a first metal layer having a first pattern density, the first metal layer being electrically connected to a plurality of nonvolatile semiconductor memories and being located on a first side of the wiring substrate;
a second metal layer having a second pattern density, the second metal layer being located on a second side of the wiring substrate;
a plurality of third metal layers disposed between the first and second metal layers and having respective third pattern densities; and
insulating layers provided between the first metal layer and a first one of the third metal layers adjacent to the first metal layer, between the second metal layer and a second one of the third metal layers adjacent to the second metal layer, and between adjacent ones of the third metal layers, wherein
a first group of metal layers includes n metal layers including the first metal layer and (n−1) adjacent third metal layers, a second group of n metal layers includes the second metal layer and (n−1) adjacent third metal layers different from the (n−1) third metal layers in the first group, a first density obtained from the first and third pattern densities of the first group of metal layers is equal to or greater than a second density obtained from the second and third pattern densities of the second group of metal layers, and a difference between the first density and the second density is 7.5% or less.