# US 9,437,532 B2 · Substrate for semiconductor package and process for manufacturing

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- Number: US 9,437,532 B2
- Document ID: US9437532B2
- Status: Granted
- Kind: B2
- Application number: 14/971,165
- Filed: 2015-12-16
- Published: 2016-04-14
- Granted: 2016-09-06
- Earliest claimed: 2012-07-05
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Tien-Szu Chen; Chun-Che Lee; Sheng-Ming Wang
- Web page: https://patentgrep.com/patent/US9437532B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H10P 76/204: {of organic photoresist masks}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H05K 2201/0367: Metallic bump or raised conductor not used as solder bump
- H05K 2201/10674: Flip chip
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

## Claims

### Claim 1

A semiconductor package, comprising:
a package substrate comprising:
a dielectric layer;
a first circuit layer disposed on or in the dielectric layer; and
a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a recess portion in the top end of the pillar;
a die; and
a plurality of solder balls disposed on the die, wherein each of the solder balls is bonded to each of the pillars and kept at the recess portion.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising an insulation material enclosing the pillars.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the first circuit layer is embedded in the dielectric layer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein each of the pillars has a top surface adapted for making external electrical connection, and a coplanarity of the top surfaces of the pillars is ±3 μm.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the recess portion is disposed at the periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein a width of the top end of the pillar is less than that of a bottom end of the pillar.

### Claim 7

A semiconductor package, comprising:
a dielectric layer;
a first circuit layer disposed on or in the dielectric layer;
a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a recess portion in the top end of the pillar;
an insulation material enclosing the pillars;
a die attached to the pillars; and
a molding compound encapsulating the die.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the insulation material is an underfill.

### Claim 9 (depends on 7)

The semiconductor package of claim 7, wherein the first circuit layer is embedded in the dielectric layer.

### Claim 10 (depends on 7)

The semiconductor package of claim 7, wherein each of the pillars has a top surface adapted for making external electrical connection, and a coplanarity of the top surfaces of the pillars is ±3 μm.

### Claim 11 (depends on 7)

The semiconductor package of claim 7, further comprising a protection layer disposed on the first circuit layer, the protection layer has an opening to expose a portion of the first circuit layer and the pillars.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein the pillars extend from the first circuit layer and beyond the protection layer.

### Claim 13 (depends on 7)

The semiconductor package of claim 7, wherein the recess portion is disposed at the periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

### Claim 14 (depends on 7)

The semiconductor package of claim 7, wherein a width of the top end of the pillar is less than that of a bottom end of the pillar.

### Claim 15

A process for making a package substrate, comprising:
(a) providing a package substrate, wherein the package substrate includes a dielectric layer and a first circuit layer disposed on or in the dielectric layer;
(b) forming a photoresist pattern adjacent to the first circuit layer, wherein the photoresist pattern has a plurality of openings;
(c) forming a plurality of pillars in the openings of the photoresist pattern; and
(d) removing a part of each of the top ends of the pillar so that each of the pillars has a recess portion in the top end of the pillar.

### Claim 16 (depends on 15)

The process of claim 15, wherein after (c), the process further comprises:
(c1) forming a top photoresist layer on a central part of each of the top surfaces of the pillars.

### Claim 17 (depends on 16)

The process of claim 16, wherein in (d), the recess portion is formed at a periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

### Claim 18 (depends on 16)

The process of claim 16, wherein in (d), a space is formed between a side surface of the top end of the pillar and a side wall of the opening of the photoresist pattern.

### Claim 19 (depends on 15)

The process of claim 15, wherein in (c), the pillar protrudes from the top surface of photoresist pattern and covers a part of the top surface of the photoresist pattern.

### Claim 20 (depends on 19)

The process of claim 19, wherein in (d), the part of the pillar which covers the part of the top surface of the photoresist pattern is removed by etching.