# US 9,437,530 B2 · Combined packaged power semiconductor device

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- Number: US 9,437,530 B2
- Document ID: US9437530B2
- Status: Granted
- Kind: B2
- Application number: 14/823,908
- Filed: 2015-08-11
- Published: 2015-12-10
- Granted: 2016-09-06
- Earliest claimed: 2010-06-18
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Yueh-Se Ho; Hamza Yilmaz; Yan Yun Xue; Jun Lu
- Web page: https://patentgrep.com/patent/US9437530B2

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/429: {being the outer leads}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 90/00: Package configurations
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07653: {changes in shapes}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

## Claims

### Claim 1

A combined packaged power semiconductor device, comprising:
a high-side (HS) MOSFET and a low-side (LS) MOSFET, each of said HS and LS MOSFETs comprising a bottom drain, a top gate and a top source;
a lead frame comprising a die paddle and a plurality of pins separated and electrically insulated from said die paddle, wherein said LS MOSFET is flipped and stacked on said die paddle forming an electrical connection between said LS source and a top surface of said die paddle, as such said LS source is electrically connected to an exposed bottom surface of said die paddle;
a first metal interconnection plate stacked on said drain of said flipped LS MOSFET, wherein said HS MOSFET directly stacked or flipped first and then stacked on said first metal interconnection plate, forming an electrical connection between said HS drain or flipped HS source and said LS drain through said first metal interconnection plate;
a second metal interconnection plate stacked and electrically connected to said source of said HS MOSFET or said drain of said flipped HS MOSFET; and
an integrated circuit (IC) controller stacked on said die paddle, said IC controller comprising a plurality of electrodes, wherein electrical connections between said plurality of pins, said plurality of electrodes on said IC controller and electrodes of said HS and said flipped LS MOSFETs are formed;
wherein a bottom surface of said IC controller is stacked on and electrically insulated from said die paddle, and
wherein said flipped LS MOSFET stacks and covers a portion of a top surface of said IC controller, forming electrical connection between a subset of said plurality of electrodes on said IC controller and said gate and a first portion of said source of said flipped LS MOSFET.

### Claim 2 (depends on 1)

The combined packaged power semiconductor device of claim 1, wherein a second portion of said source of said flipped LS MOSFET is electrically connected to a die paddle through a conductive adhesive having a predetermined thickness such that a top surface of said conductive adhesive between said second portion of said source of said flipped LS MOSFET and said die paddle and a top surface of another conductive adhesive between said first portion of said source of said flipped LS MOSFET and said IC controller are co-planar.

### Claim 3 (depends on 1)

The combined packaged power semiconductor device of claim 1, wherein a chip groove is formed on said top surface of said die paddle and wherein said IC controller is placed in said chip groove and is electrically insulated from said die paddle.