# US 9,437,517 B2 · Semiconductor apparatus including a heat dissipating member

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- Number: US 9,437,517 B2
- Document ID: US9437517B2
- Status: Granted
- Kind: B2
- Application number: 14/788,853
- Filed: 2015-07-01
- Published: 2015-10-22
- Granted: 2016-09-06
- Earliest claimed: 2013-01-07
- Assignees: Panasonic Corporation
- Applicants: Panasonic Corporation
- Inventors: Takao Ochi
- Web page: https://patentgrep.com/patent/US9437517B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/778: {in encapsulations}
- H10W 70/461: {specially adapted for cooling}
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 74/40: characterised by their materials
- H10W 90/00: Package configurations
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07554: {changes in dispositions}
- H10W 72/534: {being rectangular}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/555: {of outermost layers of multilayered bond wires, e.g. material of a coating}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space.

## Claims

### Claim 1

A semiconductor apparatus comprising:
a base having a main surface on which a terminal is disposed;
a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base;
a connection member connecting the terminal and the electrode;
an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and
a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base,
wherein the encapsulant is disposed in the space,
in a side view of the base, a peak of the connection member is located inside the space, and
the heat dissipating member does not cover any portion of the connection member in plan view.

### Claim 2 (depends on 1)

The semiconductor apparatus according to claim 1, wherein a side surface of the heat dissipating member, a side surface of the encapsulant, and a side surface of the base lie in a same plane.

### Claim 3 (depends on 2)

The semiconductor apparatus according to claim 2, wherein a top surface of the heat dissipating member and a top surface of the encapsulant lie in a same plane.

### Claim 4 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
the heat dissipating member has an H-shape in a plan view and includes a first block, a second block, and a third block,
the first block and the second block cover a region excluding (i) above the first semiconductor device and (ii) above a region in which the connection member is disposed, and
the third block connects the first block and the second block together and covers an area above the first semiconductor device.

### Claim 5 (depends on 4)

The semiconductor apparatus according to claim 4, wherein
the third block covers an area above the base, from a first side surface of the base to a second side surface of the base opposite the first side surface,
the first block is located peripheral to the first side surface of the base and covers the first side surface of the base, and
the second block is located peripheral to the second side surface of the base and covers the second side surface of the base.

### Claim 6 (depends on 5)

The semiconductor apparatus according to claim 5, wherein in the heat dissipating member, the third block is thinner than each of the first block and the second block.

### Claim 7 (depends on 5)

The semiconductor apparatus according to claim 5, wherein the third block of the heat dissipating member is thinner than the encapsulant measured from the top surface of the first semiconductor device to a top surface of the encapsulant.

### Claim 8 (depends on 1)

The semiconductor apparatus according to claim 1, wherein in a plan view, the space in the heat dissipating member is a notched section exposing a region from where the connection member is disposed to a side surface of the encapsulant.

### Claim 9 (depends on 8)

The semiconductor apparatus according to claim 8, wherein in a plan view, the notched section has a width that increases from a central region of the heat dissipating member outward.

### Claim 10 (depends on 1)

The semiconductor apparatus according to claim 1, wherein the space is an opening that opens above a region in which the connection member is disposed.

### Claim 11 (depends on 10)

The semiconductor apparatus according to claim 10, wherein in a plan view, the opening has a width that increases from a central region of the heat dissipating member outward.

### Claim 12 (depends on 10)

The semiconductor apparatus according to claim 10, wherein
the heat dissipating member extends outward beyond at least one side surface of the base, and
the at least one side surface of the base is covered by the heat dissipating member.

### Claim 13 (depends on 1)

The semiconductor apparatus according to claim 1, wherein a distance between the heat dissipating member and the first semiconductor device is in a range from 50 μm to 100 μm, inclusive.

### Claim 14 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
the encapsulant includes a first encapsulant free of a filler and a second encapsulant containing a filler,
the first encapsulant fills a gap between the heat dissipating member and the first semiconductor device, and
the second encapsulant fills a region excluding the gap between the heat dissipating member and the first semiconductor device.

### Claim 15 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
the encapsulant includes a first encapsulant containing a metal and a second encapsulant free of metal,
the first encapsulant fills a gap between the heat dissipating member and the first semiconductor device, and
the second encapsulant fills a region excluding the gap between the heat dissipating member and the first semiconductor device.

### Claim 16 (depends on 1)

The semiconductor apparatus according to claim 1, wherein the base is one of a lead frame and a second semiconductor device.

### Claim 17

A semiconductor apparatus comprising:
a base having a main surface on which a terminal is disposed;
a heat dissipating member disposed on the main surface of the base, in a region excluding the terminal;
a first semiconductor device retained on the heat dissipating member and having a top surface on which an electrode is disposed;
a connection member connecting the terminal and the electrode, the connection member having a peak portion which is the portion of the connection member located the farthest away from the base when viewed in plan;
an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member,
wherein,
the heat dissipating member has an H-shape in a plan view and includes a first block, a second block, and a third block,
the first block and the second block cover a region above the base excluding (i) above the first semiconductor device and (ii) above a region in which the connection member is disposed,
the third block connects the first block and the second block together, and
the first block and the second block of the heat dissipating member have top surfaces that are farther than the peak portion of the connection member from the base.

### Claim 18 (depends on 17)

The semiconductor apparatus according to claim 17, wherein a side surface of the heat dissipating member, a side surface of the encapsulant, and a side surface of the base lie in a same plane.

### Claim 19 (depends on 17)

The semiconductor apparatus according to claim 17, wherein the base is one of a lead frame and a second semiconductor device.