# US 9,437,516 B2 · Chip-embedded packages with backside die connection

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- Number: US 9,437,516 B2
- Document ID: US9437516B2
- Status: Granted
- Kind: B2
- Application number: 14/149,392
- Filed: 2014-01-07
- Published: 2015-07-09
- Granted: 2016-09-06
- Earliest claimed: 2014-01-07
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Ralf Otremba; Josef Höglauer; Manfred Schindler; Johannes Lodermeyer; Thorsten Scharf
- Web page: https://patentgrep.com/patent/US9437516B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/0198: {batch processes}
- H10W 72/0711: {Apparatus therefor}
- H10W 72/076: {of strap connectors}
- H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/354: {comprising polymers}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.

## Claims

### Claim 1

A semiconductor package, comprising:
a semiconductor die embedded in an insulating material, the die having a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces;
a structured metal redistribution layer disposed in the insulating material below the die; and
a metal clip embedded in the insulating material above the die and bonded to the second surface of the die,
wherein part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die,
wherein the structured metal redistribution layer is connected to terminals at the first surface of the die and connected to the part of the metal clip that extends laterally beyond the edge of the die and vertically in the first direction toward the structured metal redistribution layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising:
first conductive vias connecting the structured metal redistribution layer to the terminals at the first surface of the die; and
second conductive vias connecting the structured metal redistribution layer to the part of the metal clip that extends laterally beyond the edge of the die and vertically in the first direction toward the structured metal redistribution layer.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the structured metal redistribution layer and the metal clip comprise copper or a copper alloy.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, further comprising:
an additional semiconductor die embedded in the insulating material and spaced apart from the other die, the additional die having a first surface facing in the first direction, a second surface facing in the second direction and an edge extending between the first and second surfaces; and
third conductive vias connecting the structured metal redistribution layer to terminals at the first surface of the additional die.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the part of the metal clip that extends laterally beyond the edge of the die and vertically in the first direction toward the structured metal redistribution layer is interposed between the die and the additional die.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the insulating material is a laminate or a molding compound.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the part of the metal clip that extends laterally beyond the edge of the die and vertically in the first direction terminates at the same level within the insulating material as the first surface of the die.

### Claim 8

A semiconductor package, comprising:
a semiconductor die embedded in an insulating material, the die having opposing first and second surfaces and an edge extending between the first and second surfaces;
a structured metal redistribution layer disposed in the insulating material below the die;
first conductive vias connecting the structured metal redistribution layer to terminals at the first surface of the die;
a first metal component embedded in the insulating material above the die and bonded to the second surface of the die, part of the first metal component extending laterally beyond the edge of the die;
second conductive vias extending vertically from the structured metal redistribution layer toward the first metal component and terminating prior to the first metal component so that a gap exists between the second conductive vias and the part of the first metal component extending laterally beyond the edge of the die; and
a second metal component disposed in the gap and connecting the second conductive vias to the part of the first metal component extending laterally beyond the edge of the die.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the structured metal redistribution layer, the first conductive vias, the first metal component, the second conductive vias and the second metal component each comprise copper or a copper alloy.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein the insulating material is a laminate or a molding compound.

### Claim 11 (depends on 8)

The semiconductor package of claim 8, wherein the second metal component extends to the same level in the insulating material as the first surface of the die.

### Claim 12 (depends on 8)

The semiconductor package of claim 8, wherein the first metal component and the second metal component are of a single continuous construction.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the first metal component and the second metal component are part of a metal lead frame.

### Claim 14 (depends on 8)

The semiconductor package of claim 8, wherein the first metal component is a metal lead frame and the second metal component is a metal block.

### Claim 15 (depends on 8)

The semiconductor package of claim 8, further comprising:
an additional semiconductor die embedded in the insulating material and spaced apart from the other die, the additional die having opposing first and second surfaces and an edge extending between the first and second surfaces; and
third conductive vias connecting the structured metal redistribution layer to terminals at the first surface of the additional die.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the additional die is thinner than the other die, the semiconductor package further comprising:
a third metal component embedded in the insulating material above the additional die and bonded to the second surface of the additional die, part of the third metal component extending laterally beyond the edge of the additional die; and
fourth conductive vias extending vertically from the structured metal redistribution layer and connecting the structured metal redistribution layer to the part of the third metal component that extends laterally beyond the edge of the additional die.

### Claim 17 (depends on 15)

The semiconductor package of claim 15, further comprising:
a third metal component embedded in the insulating material above the additional die and bonded to the second surface of the additional die, part of the third metal component extending laterally beyond the edge of the additional die; and
fourth conductive vias extending vertically from the structured metal redistribution layer toward the third metal component and terminating prior to the third metal component so that an additional gap exists between the fourth conductive vias and the part of the third metal component extending laterally beyond the edge of the additional die; and
a fourth metal component disposed in the additional gap and connecting the fourth conductive vias to the part of the third metal component extending laterally beyond the edge of the additional die.

### Claim 18 (depends on 15)

The semiconductor package of claim 15, wherein the second metal component is interposed between the die and the additional die.

### Claim 19 (depends on 8)

The semiconductor package of claim 8, wherein the first metal component is electrically connected to a terminal at the second surface of the die, and wherein the second metal component and the second conductive vias provide both a thermal pathway and an electrical pathway between the structured metal redistribution layer and the first metal component.

### Claim 20

A semiconductor package, comprising:
a semiconductor die embedded in an insulating material, the die having opposing first and second surfaces and an edge extending between the first and second surfaces;
a structured metal redistribution layer disposed in the insulating material below the die;
a first metal component embedded in the insulating material above the die and bonded to the second surface of the die, part of the first metal component extending laterally beyond the edge of the die; and
a second metal component disposed under and connected to the part of the first metal component that extends laterally beyond the edge of the die, the second metal component vertically extending through the insulating material so that part of the second metal component is uncovered by the insulating material at a side of the package facing away from the second surface of the die,
wherein the first and second metal components form at least a thermal pathway from the second surface of the die to the side of the package facing away from the second surface of the die.