# US 9,437,514 B2 · Semiconductor package with coated side walls and method of manufacture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,514 B2 - Document ID: US9437514B2 - Status: Granted - Kind: B2 - Application number: 14/698,436 - Filed: 2015-04-28 - Published: 2015-11-12 - Granted: 2016-09-06 - Earliest claimed: 2014-05-07 - Assignees: Sensirion AG - Applicants: Sensirion AG - Inventors: Werner Hunziker - Web page: https://patentgrep.com/patent/US9437514B2 ## CPC - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - B81B 7/0016: {Protection against shocks or vibrations, e.g. vibration damping} - B81C 1/00261: {Processes for packaging MEMS devices (MEMS packages B81B7/0032, packaging of smart-MEMS B81C1/0023)} - B81C 1/00777: {Preserve existing structures from alteration, e.g. temporary protection during manufacturing} - B81C 1/00896: {Temporary protection during separation into individual elements} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10W 74/014: {using batch processing} - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package including an integrated device, the package having a front side, a back side and side walls linking the front and back sides, wherein each side wall is coated, to at least 80% of its area, with a coating material different from the material(s) of the back and front sides. A method of manufacturing a semiconductor package by providing an assembly containing an array of the packages, the assembly having thickness d0 and being attached to a dicing tape of thickness dd, fabricating a set of first dicing streets with width w1 and depth d1<(d0+dd), filling the first dicing streets at least partially with a coating material, and fabricating, in the coating material in each first dicing street, a second dicing street with width w2≦w1 and depth d2≧d0 but <(d0+dd). ## Claims ### Claim 1 A semiconductor package, comprising an integrated device comprising a sensitive element, a front side of a material A wherein material A represents a packaging for the integrated device, a back side of a material B opposite to the front side, side walls that link the front side and the back side, each side wall being coated with a coating material to at least 80% of its area, the coating material being different from the material A and being different from the material B, wherein one of: the front side is free from the coating material; or the coating material coated on at least one of the side walls wraps around a lateral end of the front side and covers less than 20% of the area of the front side. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein each side wall is a cut surface. ### Claim 3 (depends on 2) The semiconductor package according to claim 2, wherein the coating material one or more of: seals the cut surface to reduce emission of particles related to a dicing process used to manufacture the cut surface, and seals the cut surface to protect it. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, wherein the coating material at each side wall comprises two front ends and a side face linking the front ends, wherein each side face is a cut surface. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, wherein the coating material has a width of less than 100 micrometers. ### Claim 6 (depends on 1) The semiconductor package according to claim 1, wherein the coating material has the same width on all sidewalls of the semiconductor package. ### Claim 7 (depends on 1) The semiconductor package according to claim 1, wherein the coating material comprises at least one of glue encapsulant acryl silicone epoxy polyurethane less than 10% filler particles. ### Claim 8 (depends on 1) The semiconductor package according to claim 1, Comprising a sensitive element which is sensitive to one or more of: humidity temperature gas pressure gas flow differential pressure. ### Claim 9 (depends on 1) The semiconductor package according to claim 1, wherein the coating material coated on at least one of the side walls has on a front end a positive or negative offset from the plane of the front side and/or back side of the semiconductor package. ### Claim 10 (depends on 1) The semiconductor package according to claim 1, wherein the coating material coated on at least one of the side walls has at least one front end that has a meniscus-like shape. ### Claim 11 (depends on 1) The semiconductor package according to claim 1, wherein at least one gap extending in a direction perpendicular to the side wall is filled by a portion of the coating material. ### Claim 12 (depends on 1) The semiconductor package according to claim 1, wherein a front end of the coating material coated on at least one of the side walls is covered by a lateral extension of the front side material A or by a lateral extension of the back side material B. ### Claim 13 A method for manufacturing a semiconductor package, comprising: (a) providing a semiconductor package assembly containing an array of semiconductor packages for manufacturing a plurality of semiconductor packages, each semiconductor package comprising an integrated device comprising a sensitive element, a front side representing a packaging for the integrated device, a front side of the semiconductor package assembly comprising access openings to the sensitive elements, the semiconductor package assembly having a thickness d0 and being attached to a dicing tape of thickness dd with the front side of the semiconductor package assembly facing the dicing tape, (b) fabricating a set of first dicing streets around semiconductor packages or groups of semiconductor packages with a width w1 and a depth d1<(d0+dd) from a backside of the semiconductor package assembly, (c) filling the set of first dicing streets at least partially with a coating material, (d) fabricating, in the coating material in each first dicing street of the set, a second dicing street with a width w2<=w1 and a depth d2>=d0 and d2<(d0+dd), resulting in semiconductor packages with side walls, each side wall being coated with the coating material to at least 80% of its area. ### Claim 14 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the semiconductor package assembly has a front side of material A and back side of material B and wherein the coating material is different from material A and from material B. ### Claim 15 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the set of first dicing streets is filled with the coating material by applying the coating material in the set of first dicing streets. ### Claim 16 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the set of first dicing streets is filled with the coating material by depositing the coating material in areas outside of but in contact with the set of first dicing streets and filling the set of first dicing streets by means of capillary force. ### Claim 17 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the second dicing street in the coating material in each first dicing street of the set is fabricated in the center of each first dicing street of the set in such a way that a plurality of individual semiconductor packages having side walls that are coated by coating material of essentially equal width are formed. ### Claim 18 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the depth of the set of first dicing streets is equal to the thickness of the semiconductor package assembly. ### Claim 19 (depends on 13) The method for manufacturing a semiconductor package of claim 13, wherein the depth of the set of first dicing streets is smaller than the thickness of the semiconductor package assembly.