# US 9,437,513 B2 · Electrically insulating thermal interface on the discontinuity of an encapsulation structure

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- Number: US 9,437,513 B2
- Document ID: US9437513B2
- Status: Granted
- Kind: B2
- Application number: 14/501,070
- Filed: 2014-09-30
- Published: 2015-04-16
- Granted: 2016-09-06
- Earliest claimed: 2013-10-15
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Edward Fuergut; Manfred Mengel
- Web page: https://patentgrep.com/patent/US9437513B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 40/778: {in encapsulations}
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 70/427: {Bent parts}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 40/251: {Organics}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/016: {using moulds}
- H10W 74/10: characterised by their shape or disposition
- H10W 76/17: characterised by their materials
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

## Claims

### Claim 1

Electronic semiconductor package, comprising:
an electronic chip;
a carrier coupled to the electronic chip;
an encapsulation structure at least partially encapsulating the electronic chip and partially encapsulating the carrier, wherein the encapsulation structure has a discontinuity; and
an electrically insulating thermal interface structure, which covers at least a part of the discontinuity and a volume connected thereto, which volume adjoins an exposed surface section of the carrier, wherein the thermal interface structure electrically decouples at least a part of the carrier with respect to a surrounding of the carrier,
wherein the discontinuity is an annular discontinuity, which surrounds a surface section of the carrier circumferentially and which extends into the encapsulation structure,
wherein side walls of the encapsulation structure surrounding the discontinuity are inclined by an angle in a range of between 5° and 35° with respect to a vertical extension into the encapsulation structure.

### Claim 2 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the thermal interface structure is in direct contact with the carrier within the discontinuity.

### Claim 3 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the thermal interface structure has a thickness in a range between 20 μm and 500 μm.

### Claim 4 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the thermal interface structure comprises a solid body layer of a matrix with filling particles embedded therein.

### Claim 5 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the thermal interface structure comprises a viscous formless material.

### Claim 6 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the encapsulation structure has multiple discontinuities, which are at least partially covered by the electrically insulating thermal interface structure.

### Claim 7 (depends on 1)

Electronic semiconductor package in accordance with claim 1, wherein the thermal interface structure has a higher thermal conductivity than the encapsulation structure.

### Claim 8

Electronic arrangement, comprising:
an electronic semiconductor package, comprising:
an electronic chip;
a carrier coupled to the electronic chip;
an encapsulation structure at least partially encapsulating the electronic chip and partially encapsulating the carrier, wherein the encapsulation structure has a discontinuity; and
an electrically insulating thermal interface structure, which covers at least a part of the discontinuity and a volume connected thereto, which volume adjoins an exposed surface section of the carrier, wherein the thermal interface structure electrically decouples at least a part of the carrier with respect to a surrounding of the carrier;
wherein the discontinuity is an annular discontinuity, which surrounds a surface section of the carrier circumferentially and which extends into the encapsulation structure,
wherein side walls of the encapsulation structure surrounding the discontinuity are inclined by an angle in a range of between 5° and 35° with respect to a vertical extension into the encapsulation structure.
a heat dissipation element, which is connected externally to the thermal interface structure to provide a thermal coupling with the carrier.