# US 9,437,511 B2 · Method and structure for wafer-level packaging

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- Number: US 9,437,511 B2
- Document ID: US9437511B2
- Status: Granted
- Kind: B2
- Application number: 14/964,869
- Filed: 2015-12-10
- Published: 2016-06-16
- Granted: 2016-09-06
- Earliest claimed: 2014-12-11
- Assignees: Nantong Fujitsu Microelectronics Co., Ltd.
- Applicants: Nantong Fujitsu Microelectronics Co., Ltd.
- Inventors: Jiangen Shi
- Web page: https://patentgrep.com/patent/US9437511B2

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 20/4421: {the principal metal being copper}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/147: {the encapsulations being multilayered}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the wafer. The method further includes forming a plurality of through holes in the connections stems; forming a protective layer covering the wafer with a plurality of positions for planting soldering balls exposed. The protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes. The upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers. The method also includes forming soldering balls on the positions for planting soldering balls and finally, forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes.

## Claims

### Claim 1

A method for wafer-level packaging, comprising:
providing a semiconductor wafer having a plurality of semiconductor chips and connection stems, wherein the connection stems are under scribe grooves of the wafer between semiconductor chips;
forming a plurality of through holes in the connection stems;
forming a protective layer covering the wafer and exposing positions for planting soldering balls;
forming soldering balls on the positions for planting soldering balls; and
forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes, wherein:
the protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes; and
the upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers.

### Claim 2 (depends on 1)

The method according to claim 1, wherein forming the protective layer further includes:
providing a softened protective material; and
flowing the softened protective material from one side of the wafer to an opposite side of the wafer through the through holes to cover the wafer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the protective layer is made of a resin material.

### Claim 4 (depends on 1)

The method according to claim 1, wherein each semiconductor chip on the wafer includes:
an electrode;
a passivation layer formed on the electrode and on the semiconductor chip with an opening exposing a portion of the electrode; and
a distribution metal layer formed on the passivation layer and electrically connecting to the electrode in the opening formed in the passivation layer.

### Claim 5 (depends on 4)

The method according to claim 4, wherein each semiconductor chip on the wafer further includes a copper pillar formed on the distribution metal layer and a top surface of the copper pillar defines a corresponding position for planting soldering balls.

### Claim 6 (depends on 4)

The method according to claim 4, wherein:
the passivation layer has a single layer structure including a first passivation layer; and
the opening is formed in the first passivation layer.

### Claim 7 (depends on 4)

The method according to claim 4, wherein:
the passivation layer has a double layer structure including a first passivation layer and a second passivation layer with the second passivation layer formed on the first passivation layer;
the opening is formed by a first opening in the first passivation layer and a second opening in the second passivation layer; and
the second opening formed in the second passivation layer is on the top of the first opening formed in the first passivation layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the through holes are formed by directly penetrating through the corresponding connection stems.

### Claim 9 (depends on 1)

The method according to claim 1, wherein forming the through holes further includes:
forming blind holes with a pre-defined depth from a front side of the corresponding connection stems; and
polishing the wafer from the back side until the blind holes form through holes.

### Claim 10 (depends on 1)

The method according to claim 1, wherein forming a plurality of packaged individual chip structures by cutting the wafer along the connection stems further includes cutting the protective layer along the connection stems.

### Claim 11

A packaged semiconductor wafer, comprising:
a plurality of semiconductor chips and connection stems with the connection stems located under scribe grooves of the wafer between semiconductor chips;
a plurality of through holes formed in the connection stems;
a plurality of copper pillars formed on the wafer;
a plurality of soldering balls planted on top surfaces of the plurality of copper pillars; and
a protective layer covering the wafer with the soldering ball exposed; wherein:
the connection stems are connection parts in the wafer under a plurality of scribe grooves pre-defined between the plurality of semiconductor chips;
the protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the plurality of through holes penetrating the connection stems; and
the upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers.

### Claim 12 (depends on 11)

The packaged semiconductor wafer according to claim 11, wherein each semiconductor chip further includes:
an electrode formed on a top surface of the semiconductor wafer;
a passivation layer formed on the semiconductor chip and on the electrode with an opening exposing a portion of the electrode;
a re-distribution metal layer formed on the passivation layer and electrically connecting to the electrode in the opening formed in the passivation layer; wherein:
the re-distribution layer is electrically contacted with the copper pillar formed on the re-distribution layer.

### Claim 13 (depends on 11)

The packaged semiconductor wafer according to claim 11, wherein:
the passivation layer has a single layer structure including a first passivation layer; and
the opening is formed in the first passivation layer.

### Claim 14 (depends on 11)

The packaged semiconductor wafer according to claim 11, wherein:
the passivation layer has a double layer structure including a first passivation layer and a second passivation layer with the second passivation layer formed on the first passivation layer;
the opening is formed by an opening in the first passivation layer and an opening in the second passivation layer; and
the opening formed in the second passivation layer is on the top of the opening formed in the first passivation layer.

### Claim 15 (depends on 11)

A packaged semiconductor chip structure cutting from the packaged semiconductor wafer according to claim 11, comprising:
an electrode formed on a top surface of the semiconductor chip;
a passivation layer formed on the semiconductor chip and on the electrode with an opening exposing a portion of the electrode;
a distribution metal layer formed on the passivation layer and electrically contacted with the electrode in the opening formed in the passivation layer;
a copper pillar formed on the distribution metal layer;
a soldering ball planted on a top surface of the copper pillar; and
a protective layer covering the above components with the soldering ball exposed; wherein:
the protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers covering a portion of the edges of the semiconductor chip structure; and
the upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers.

### Claim 16 (depends on 15)

The packaged semiconductor chip structure according to claim 15, wherein:
the passivation layer has a single layer structure including a first passivation layer; and
the opening is formed in the first passivation layer.

### Claim 17 (depends on 15)

The packaged semiconductor chip structure according to claim 15, wherein:
the passivation layer has a double layer structure including a first passivation layer and a second passivation layer with the second passivation layer formed on the first passivation layer;
the opening is formed by an opening in the first passivation layer and an opening in the second passivation layer; and
the opening formed in the second passivation layer is on the top of the opening formed in the first passivation layer.

### Claim 18 (depends on 15)

The packaged semiconductor chip structure according to claim 15, wherein:
a connection stem residue is present at an edge of the semiconductor chip structure; and
the connection stem residue is covered by a middle protective layer formed in a corresponding through hole with a dimension of the through hole smaller than a dimension of the connection stem.

### Claim 19 (depends on 15)

The packaged semiconductor chip structure according to claim 15, wherein:
an edge of the semiconductor chip structure is directly covered by a middle protective layer formed in a corresponding through hole with a dimension equal to a dimension of the connection stem.