# US 9,437,508 B2 · Method for manufacturing semiconductor device and semiconductor device

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- Number: US 9,437,508 B2
- Document ID: US9437508B2
- Status: Granted
- Kind: B2
- Application number: 14/381,133
- Filed: 2013-03-06
- Published: 2015-02-05
- Granted: 2016-09-06
- Earliest claimed: 2012-05-15
- Assignees: Panasonic Intellectual Property Management Co., Ltd.
- Applicants: Panasonic Corporation
- Inventors: Zyunya Tanaka; Masanori Minamio
- Web page: https://patentgrep.com/patent/US9437508B2

## CPC

- H10W 76/161: {Containers comprising no base}
- H10W 40/778: {in encapsulations}
- H10W 70/429: {being the outer leads}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/534: {being rectangular}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is placed on a working table (3) with an opening (30) formed at the bottom of the case (2). Subsequently, as shown in FIG. 2(B), a plurality of packages (6,6,6) including second terminals (4) are placed on the working table (3) through the opening (30) of the case (2), forming a clearance (31) between the first terminal (1) and the second terminal (4). As shown in FIG. 2(C), a bonding material (7) is disposed in the clearance (31) so as to electrically connect the first terminal (1) and the second terminal (4). Thus, the exposed surfaces of the packages (6,6,6) in the opening (30) of the case (2) are aligned at the same height, thereby reducing variations in thermal resistance among the packages (6,6,6).

## Claims

### Claim 1

A method for manufacturing a semiconductor device including a plurality of packages disposed in a resin-molded case, the package containing a power semiconductor element,
the method comprising:
placing a bottom of the case on a working table with an opening formed at the bottom, the case including a first terminal with one end internally drawn along the bottom of the case for connecting to the power semiconductor element;
placing the package on the working table through the opening of the case, the package including a second terminal connected to the power semiconductor element, disposing a first faying surface that is a top surface of the first terminal of the case and a second faying surface that is an undersurface of the second terminal of the package in such a manner that the first faying surface and the second faying surface are opposed to each other, and forming a clearance between the first faying surface and the second faying surface; and
electrically connecting the first terminal and the second terminal with a bonding material disposed in the clearance.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the first terminal and the second terminal are joined to each other by heating and melting Sn solder used as a bonding material.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the second terminal is plated with Sn used as a principal component.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the package includes a third terminal drawn in a direction that separates from the working table along the depth direction of the case, and a control board including a circuit configured to output a driving signal to the power semiconductor element is electrically connected to the third terminal before or after the package is placed on the working table.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein one of the first terminal and the second terminal is composed of one of Cu and a Cu alloy.