# US 9,437,506 B2 · Semiconductor defect characterization

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- Number: US 9,437,506 B2
- Document ID: US9437506B2
- Status: Granted
- Kind: B2
- Application number: 14/271,331
- Filed: 2014-05-06
- Published: 2014-11-13
- Granted: 2016-09-06
- Earliest claimed: 2013-05-10
- Assignees: Lattice Semiconductor Corporation
- Applicants: Lattice Semiconductor Corporation
- Inventors: Uwe Hessinger; Brett Schafman; Wendy Chan
- Web page: https://patentgrep.com/patent/US9437506B2

## CPC

- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects.

## Claims

### Claim 1

A method of semiconductor manufacture, comprising:
in a computer for analyzing a wafer having a number of die (N), counting a number (H) of the die that are included in both a subset of the N die, with a number (D) members, having a defect, as identified from an inspection layer analysis of the wafer, and which also are included in a subset of the N die, which are failing, having a number of failing die (F) identified from a fault test of the wafer;
in the computer, dividing H into a number (Hk) of die that are postulated to have a defect that caused a die failure and into a number (Hb) of the die that are postulated to have a defect that did not cause a die failure, wherein the division is based upon the numbers H, D, F, and N, and H=Hk+Hb;
in the computer, calculating a number (Hr) of die that has the same proportionality to F as does D to N;
in the computer, computing a probability (P(H)) of H occurring and a probability (P(Hr)) of Hr occurring; and
adjusting a wafer manufacturing step based at least on P(H) and P(Hr).

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
in the computer, computing a confidence factor based upon a ratio of P(H) and P(Hr).

### Claim 3 (depends on 2)

The method of claim 2, wherein computing the confidence factor is further based upon a logarithm of the ratio.

### Claim 4 (depends on 2)

The method of claim 2, further comprising: in the computer, calculating a confidence-factor-adjusted yield based upon the confidence factor and Hk.

### Claim 5 (depends on 4)

The method of claim 4, wherein the calculation of the confidence-factor-adjusted yield is further based upon N.

### Claim 6 (depends on 2)

The method of claim 2, further comprising repeating the counting, dividing, and computing steps for additional inspection layers for the wafer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising identifying the inspection layers that have confidence factors greater than a threshold.

### Claim 8 (depends on 7)

The method of claim 7, wherein the threshold is at one or greater.

### Claim 9 (depends on 7)

The method of claim 7, further comprising analyzing a wafer map for each of the identified inspection layers, wherein each wafer map classifies the die according to the corresponding inspection layer analysis and fault testing.

### Claim 10 (depends on 9)

The method of claim 9, further comprising adjusting the wafer manufacturing process step based upon the confidence-factor-adjusted yield.

### Claim 11 (depends on 1)

The method of claim 1, wherein computing the probability P(H) comprises using a hypergeometric function.

### Claim 12 (depends on 9)

The method of claim 9, wherein the hypergeometric function equals (F!/(H!*(F−H)!))*((N−F)!/((D−H)!*(N−F−D+H)!))/(N!/(D!*(N−D)!)).

### Claim 13 (depends on 1)

The method of claim 1, wherein computing the probability P(Hr) comprises using a hypergeometric function.

### Claim 14

A system, comprising:
a computer configured to:
count a number (H) of the die on a wafer that are included in both a number D of die on the wafer that have a defect as identified from an inspection layer analysis and included in a number (F) of failing die on the wafer identified from a fault test;
divide the number H into a number (Hk) of die that are postulated to have a defect that caused a die failure and into a number (Hb) of the die that are postulated to have a defect that did not cause a die failure, wherein the division is based upon the numbers H, D, F, and N;
calculate a number (Hr) of die that has the same proportionality to F as the proportionality of D to N; and
compute a probability (P(H)) of H occurring and a probability (P(Hr)) of Hr occurring.

### Claim 15 (depends on 14)

The system of claim 14, wherein the computer is further configured to compute a confidence factor based upon a ratio between P(H) and P(Hr).

### Claim 16 (depends on 15)

The system of claim 15, wherein the computer is further configured to compute the confidence factor based upon a logarithm of the ratio.

### Claim 17 (depends on 14)

The system of claim 14, wherein the computer is further configured to repeat the counting, dividing, and computing steps for additional inspection layers for the wafer.

### Claim 18 (depends on 1)

The method of claim 1, further comprising:
subsequent to a manufacturing step for a wafer having a number N of die;
performing an inspection analysis to identify the number D of die on the wafer with a defect; and
subsequent to a completion of the manufacturing of the die on the wafer, testing an operability of the die to identify the number F of the die that failed the testing.