Vertical FETs with variable bottom spacer recess

A method of forming a variable spacer in a vertical transistor device, the method comprising:

• forming a first source/drain of a first transistor on a substrate;
• forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain;
• depositing a spacer material on the first source/drain and the second source/drain;
• forming first channels in the spacer material extending from the first source/drain and second channels in the spacer material extending from the second source/drain;
• depositing a first block mask on spacer material of the first transistor;
• recessing the spacer material of the second transistor to form a spacer on the second source/drain and around the second channels, and then removing the first block mask;
• depositing a second block mask on spacer arranged on the second source/drain;
• and
• recessing the spacer material arranged of the first transistor to form a spacer on the first source/drain and around the first channels, and then removing the second block mask;
• wherein the spacer of the first transistor is different in thickness than the spacer of the first transistor.

A semiconductor device, comprising:

• a first source/drain of a first transistor arranged on a substrate;
• a second source/drain of a second transistor arranged on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain;
• a first spacer arranged on the first source/drain, a first channel extending from the first source/drain through the first spacer;
• a second spacer arranged on the second source/drain, a second channel extending from the second source/drain through the second spacer, the first spacer and the second spacer having different thicknesses;
• and
• a first gate stack arranged along sidewalls of the first channel and in contact with the first spacer, and a second gate stack arranged along sidewalls of the second channel and in contact with the second spacer.