# US 9,437,502 B1 · Method to form stacked germanium nanowires and stacked III-V nanowires

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,502 B1
- Document ID: US9437502B1
- Status: Granted
- Kind: B1
- Application number: 14/738,316
- Filed: 2015-06-12
- Granted: 2016-09-06
- Earliest claimed: 2015-06-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Pouya Hashemi; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9437502B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A first sacrificial gate structure is formed over a first fin stack and a second sacrificial gate structure is formed over a second fin stack. The first and second fin stacks include alternating layers of a III-V compound semiconductor material portion and a germanium material portion. Source/drain structures are formed adjacent the first and second sacrificial gate structures. The first sacrificial structure is removed to provide a first gate cavity. Exposed III-V compound semiconductor portions in the first gate cavity are removed to suspend a portion of each germanium material portion. A first functional gate structure is formed in the first gate cavity. The second sacrificial structure is removed to provide a second gate cavity. Exposed germanium material portions are removed to suspend a portion of each III-V compound semiconductor material portion of the second fin stack. A second functional gate structure is formed in the second gate cavity.

## Claims

### Claim 1

A method of forming a semiconductor structure, said method comprising:
forming a first sacrificial gate structure straddling over a portion of a first fin stack and a second sacrificial gate structure straddling over a portion of a second fin stack, wherein said first and second fin stacks comprise alternating layers of a III-V compound semiconductor material portion and a germanium material portion;
forming a first source/drain structure on other portions of said first fin stack and adjacent said first sacrificial gate structure and a second source/drain structure on other portions of said second fin stack and adjacent said second sacrificial gate structure;
removing said first sacrificial structure selective to said second sacrificial gate structure to provide a first gate cavity;
removing each exposed III-V compound semiconductor portion of said first fin stack in said first gate cavity to provide suspended germanium nanowires that comprise a portion of each germanium material portion of said first fin stack;
forming a first functional gate structure in said first gate cavity and surrounding each suspended germanium nanowire;
removing said second sacrificial structure selective to said first functional gate structure to provide a second gate cavity;
removing each exposed germanium material portion of said second fin stack in said second gate cavity to provide suspended III-V compound semiconductor nanowires that comprise a portion of each III-V compound semiconductor material portion of said second fin stack; and
forming a second functional gate structure in said second gate cavity and surrounding each suspended III-V compound semiconductor nanowire.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first fin stack is formed on a first portion of a germanium layer and said second fin stack is formed on a second portion of said germanium layer and wherein said first and second fin stacks comprise alternating layers, of from bottom to top, of said III-V compound semiconductor material portion and said germanium material portion.

### Claim 3 (depends on 2)

The method of claim 2, wherein during said removing each exposed germanium material portion in said second device region, a recessed region is provided in said germanium layer, and wherein a lower portion of said second functional gate structure fills said recessed region.

### Claim 4 (depends on 1)

The method of claim 1, wherein said first fin stack is formed on a first portion of a III-V compound semiconductor layer and said second fin stack is formed on a second portion of said III-V compound semiconductor layer and wherein said first and second fin stacks comprise alternating layers, of from bottom to top, of said germanium material portion and said III-V compound semiconductor material portion.

### Claim 5 (depends on 4)

The method of claim 4, wherein during said removing each exposed III-V compound semiconductor portion in said first device region, a recessed region is provided in said III-V compound semiconductor layer, and wherein a lower portion of said first functional gate structure fills said recessed region.

### Claim 6 (depends on 1)

The method of claim 1, wherein said first fin stack and said second fin stack are formed by:
providing a material stack comprising alternating layers of a III-V compound semiconductor material and a germanium material; and
patterning said material stack.

### Claim 7 (depends on 6)

The method of claim 6, wherein said providing said material stack comprises epitaxial deposition said alternating layers of said III-V compound semiconductor material and said germanium material.

### Claim 8 (depends on 6)

The method of claim 6, wherein said patterning comprises a sidewall image transfer process.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a dielectric spacer on sidewall surfaces of said first sacrificial gate structure and said second sacrificial gate structure prior to forming said first and second source/drain structures.

### Claim 10 (depends on 1)

The method of claim 1, wherein said first source/drain structure and said second source/drain structure are formed utilizing at least an epitaxial growth process.

### Claim 11

A method of forming a semiconductor structure, said method comprising:
forming a first sacrificial gate structure straddling over a portion of a first fin stack and a second sacrificial gate structure straddling over a portion of a second fin stack, wherein said first and second fin stacks comprise alternating layers of a III-V compound semiconductor material portion and a germanium material portion;
forming a first source/drain structure on other portions of said first fin stack and adjacent said first sacrificial gate structure and a second source/drain structure on other portions of said second fin stack and adjacent said second sacrificial gate structure;
removing said second sacrificial structure selective to said first sacrificial gate structure to provide a second gate cavity;
removing each exposed germanium material portion of said second fin stack in said second gate cavity to provide suspended III-V compound semiconductor nanowires that comprise a portion of each III-V compound semiconductor material portion of said second fin stack;
forming a second functional gate structure in said second gate cavity and surrounding each suspended III-V compound semiconductor nanowire;
removing said first sacrificial structure selective to said second functional gate structure to provide a first gate cavity;
removing each exposed III-V compound semiconductor portion of said first fin stack in said first gate cavity to provide suspended germanium nanowires that comprise a portion of each germanium material portion of said first fin stack; and
forming a first functional gate structure in said first gate cavity and surrounding each suspended germanium nanowire.

### Claim 12 (depends on 11)

The method of claim 11, wherein said first fin stack is formed on a first portion of a germanium layer and said second fin stack is formed on a second portion of said germanium layer and wherein said first and second fin stacks comprise alternating layers, of from bottom to top, of said III-V compound semiconductor material portion and said germanium material portion.

### Claim 13 (depends on 12)

The method of claim 12, wherein during said removing each exposed germanium material portion in said second device region, a recessed region is provided in said germanium layer, and wherein a lower portion of said second functional gate structure fills said recessed region.

### Claim 14 (depends on 11)

The method of claim 11, wherein said first fin stack is formed on a first portion of a III-V compound semiconductor layer and said second fin stack is formed on a second portion of said III-V compound semiconductor layer and wherein said first and second fin stacks comprise alternating layers, of from bottom to top, of said germanium material portion and said III-V compound semiconductor material portion.

### Claim 15 (depends on 14)

The method of claim 14, wherein during said removing each exposed III-V compound semiconductor portion in said first device region, a recessed region is provided in said III-V compound semiconductor layer, and wherein a lower portion of said first functional gate structure fills said recessed region.

### Claim 16 (depends on 11)

The method of claim 11, wherein said first fin stack and said second fin stack are formed by
providing a material stack comprising alternating layers of a III-V compound semiconductor material and a germanium material; and
patterning said material stack.

### Claim 17 (depends on 16)

The method of claim 16, wherein said providing said material stack comprises epitaxial deposition said alternating layers of said III-V compound semiconductor material and said germanium material.

### Claim 18 (depends on 16)

The method of claim 16, wherein said patterning comprises a sidewall image transfer process.

### Claim 19 (depends on 11)

The method of claim 11, further comprising forming a dielectric spacer on sidewall surfaces of said first sacrificial gate structure and said second sacrificial gate structure prior to forming said first and second source/drain structures.

### Claim 20 (depends on 11)

The method of claim 11, wherein said first source/drain structure and said second source/drain structure are formed utilizing at least an epitaxial growth process.