# US 9,437,501 B1 · Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

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- Number: US 9,437,501 B1
- Document ID: US9437501B1
- Status: Granted
- Kind: B1
- Application number: 14/861,326
- Filed: 2015-09-22
- Granted: 2016-09-06
- Earliest claimed: 2015-09-22
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: International Business Machines Corporation; GlobalFoundries, Inc.
- Inventors: Kangguo Cheng; Xin Miao; Ruilong Xie; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US9437501B1

## CPC

- H10D 62/121: {oriented parallel to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 30/224: {of a cluster, e.g. using a gas cluster ion beam}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

## Claims

### Claim 1

A method of making a nanowire device, the method comprising:
disposing a first nanowire stack of a first transistor over a substrate, the first nanowire stack comprising alternating layers of a first semiconducting material and a second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the first nanowire stack;
disposing a second nanowire stack of a second transistor over the substrate, the second nanowire stack comprising alternating layers of the first semiconducting material and the second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the second nanowire stack;
forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack;
oxidizing a portion of the first nanowire stack within the first gate spacer of the first gate region; and
removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first nanowire stack and the second nanowire stack are formed simultaneously before oxidizing a portion of the first nanowire stack.

### Claim 3 (depends on 1)

The method of claim 1, further comprising filling the first gate region and the second gate region with a high-k metal gate material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first semiconducting material comprises silicon germanium, and the second semiconducting material comprises silicon.

### Claim 5 (depends on 1)

The method of claim 1, wherein oxidizing a portion of the first nanowire stack comprises a gas cluster ion beam process.

### Claim 6 (depends on 1)

The method of claim 1, wherein oxidizing a portion of the first nanowire stack comprises a room temperature oxidation process.

### Claim 7 (depends on 1)

The method of claim 1, wherein oxidizing a portion of the first nanowire stack comprises bombarding the first nanowire stack with ionized oxygen atoms, ionized oxygen molecules, or a combination thereof.

### Claim 8

A method of making a nanowire device, the method comprising:
disposing a first nanowire stack of a first transistor over a substrate, the first nanowire stack comprising alternating layers of a first semiconducting material and a second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the first nanowire stack;
disposing a second nanowire stack of a second transistor over the substrate, the second nanowire stack comprising alternating layers of the first semiconducting material and the second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the second nanowire stack;
forming a first gate on the first nanowire stack and a second gate on the second nanowire stack, the first and second gates comprising a sacrificial gate material;
removing the sacrificial gate material from the first gate and the second gate;
disposing a mask over the second transistor;
oxidizing a portion of the first nanowire stack;
removing the mask and the first semiconducting material from the first nanowire stack and the second nanowire stack; and
filling the first gate and the second gate with a high-k metal gate material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the sacrificial gate material comprises amorphous silicon, polysilicon, or a combination thereof.

### Claim 10 (depends on 8)

The method of claim 8, wherein oxidizing a portion of the first nanowire stack comprises bombarding the first nanowire stack with ionized oxygen atoms, ionized oxygen molecules, or a combination thereof.

### Claim 11 (depends on 8)

The method of claim 8, wherein first semiconducting material comprises silicon germanium, and the second semiconducting material comprises silicon.

### Claim 12 (depends on 8)

The method of claim 8, wherein the first and second transistors comprise a different number of active nanowires.

### Claim 13

A nanowire device, comprising:
a first transistor comprising a first gate disposed over a portion of a first nanowire stack, the first nanowire stack comprising a first semiconducting nanowire and a dielectric nanowire; and
a second transistor comprising a second gate disposed over a portion of a second nanowire stack, the second nanowire stack comprising a second semiconducting nanowire and a third semiconducting nanowire.

### Claim 14 (depends on 13)

The nanowire device of claim 13, wherein the first nanowire stack and the second nanowire stack are disposed over an oxide layer of a substrate.

### Claim 15 (depends on 13)

The nanowire device of claim 13, wherein the first, second, and third semiconducting nanowires comprise silicon, silicon germanium, or a combination thereof.

### Claim 16 (depends on 13)

The nanowire device of claim 13, wherein the dielectric nanowire comprises silicon dioxide.

### Claim 17 (depends on 13)

The nanowire device of claim 13, wherein the first transistor further comprises a source region and a drain region on opposing sides of the first gate.

### Claim 18 (depends on 17)

The nanowire device of claim 17, wherein the source region and the drain region comprise epitaxial growth disposed over the first nanowire stack.

### Claim 19 (depends on 18)

The nanowire device of claim 18, wherein the dielectric nanowire comprises a semiconducting portion beneath the epitaxial growth.

### Claim 20 (depends on 13)

The nanowire device of claim 13, wherein the dielectric nanowire comprises a dielectric portion and a semiconducting portion, the semiconducting portion being disposed beneath an epitaxial growth forming a source/drain region.