# US 9,437,493 B2 · Method of forming a semiconductor die

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- Number: US 9,437,493 B2
- Document ID: US9437493B2
- Status: Granted
- Kind: B2
- Application number: 14/849,779
- Filed: 2015-09-10
- Published: 2016-01-07
- Granted: 2016-09-06
- Earliest claimed: 2010-01-18
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Gordon M. Grivna; Michael J. Seddon
- Web page: https://patentgrep.com/patent/US9437493B2

## CPC

- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 50/242: {of Group IV materials}
- H10P 50/244: {comprising alternated and repeated etching and passivation steps}
- H10P 50/73: {using masks for insulating materials}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10W 90/00: Package configurations
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10H 20/819: characterised by their shape, e.g. curved or truncated substrates
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

## Claims

### Claim 1

A method of forming a semiconductor die comprising:
providing a semiconductor wafer including a bulk semiconductor substrate having a top surface and a bottom surface;
forming a plurality of semiconductor die on the top surface of the silicon bulk semiconductor substrate with at least one die of the plurality of semiconductor die having regions for forming two substantially straight sides that intersect to form a first corner having a substantially curved shape and other regions for forming one or more other corners of the semiconductor die having a different shape than the first corner;
forming a singulation region as a region of the semiconductor wafer that is between the semiconductor die; and
using a dry etch to form an opening through the silicon bulk semiconductor substrate to simultaneously singulate the plurality of semiconductor die and form at least the first corner, the one or more other corners, and the two substantially straight sides.

### Claim 2 (depends on 1)

The method of claim 1 wherein using the dry etch includes forming two other sides of the semiconductor die that intersect to form a substantially right angle.

### Claim 3 (depends on 1)

The method of claim 1 wherein using the dry etch includes forming the openings completely through the semiconductor wafer and the semiconductor die along with the bulk semiconductor substrate.

### Claim 4 (depends on 1)

The method of claim 1 wherein providing the semiconductor wafer including the bulk semiconductor substrate includes providing the bulk semiconductor substrate as a the bulk silicon semiconductor substrate.