# US 9,437,491 B2 · Method of forming chip with through silicon via electrode

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- Number: US 9,437,491 B2
- Document ID: US9437491B2
- Status: Granted
- Kind: B2
- Application number: 14/791,265
- Filed: 2015-07-03
- Published: 2015-10-29
- Granted: 2016-09-06
- Earliest claimed: 2013-01-23
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Ming-Tse Lin; Chu-Fu Lin; Chien-Li Kuo; Yung-Chang Lin
- Web page: https://patentgrep.com/patent/US9437491B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10P 14/40: of conductive or resistive materials
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0257: {comprising using a sacrificial placeholder, e.g. using a sacrificial plug}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/635: {Through-vias}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10D 1/692: {Electrodes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/29: Bond pads specially adapted therefor
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

## Claims

### Claim 1

A method of forming a chip with a though-silicon-via (TSV) electrode, comprising:
providing a substrate, wherein the substrate has a first surface and a second surface;
performing a thinning process from the second surface of the substrate thereby making the second surface become a third surface;
forming a penetration via which penetrates through the first surface and the third surface;
forming a patterned material layer on the third surface of the substrate, wherein the patterned material layer has an opening exposing the penetration via; and
simultaneously filling a conductive layer into the penetration via and the opening such that the conductive layer in the penetration via becomes a TSV electrode and the conductive layer in the opening becomes a surface conductive layer, wherein the surface conductive layer is a redistribution layer.

### Claim 2 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, further comprising:
after forming the conductive layer, removing the patterned material layer.

### Claim 3 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, further comprising forming an integrated passive device (IPD),
wherein the IPD comprises the surface conductive layer.

### Claim 4 (depends on 3)

The method of forming a chip with a TSV electrode according to claim 3, wherein the IPD comprises a bumper, a resistor, a capacitor, an inductor or an antenna.

### Claim 5 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, further comprising:
before forming the patterned material layer, forming a seed layer on the third surface and a surface of the penetration via.

### Claim 6 (depends on 5)

The method of forming a chip with a TSV electrode according to claim 5, further comprising:
after forming the conductive layer, removing the seed layer not covered by the conductive layer.

### Claim 7 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, further comprising:
before forming the patterned material layer, forming a barrier layer on the third surface and a surface of the penetration via.

### Claim 8 (depends on 7)

The method of forming a chip with a TSV electrode according to claim 7, further comprising:
after forming the conductive layer, removing the barrier layer not covered by the conductive layer.

### Claim 9 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, wherein the step of forming the penetration via comprises:
after the thinning process, performing an etching process on the third surface to form the penetration via.

### Claim 10 (depends on 1)

The method of forming a chip with a TSV electrode according to claim 1, wherein the step of forming the penetration via comprises:
before the thinning process, performing an etching process on the first surface to form a via;
filling a sacrificial layer into the via;
when performing the thinning process, exposing the sacrificial layer; and
removing the sacrificial layer in the via such that the via becomes the penetration via.

### Claim 11

A method of forming a chip with a though-silicon-via (TSV) electrode, comprising:
providing a substrate, wherein the substrate has a first surface and a second surface;
performing a thinning process from the second surface of the substrate thereby making the second surface become a third surface;
forming a penetration via which penetrates through the first surface and the third surface;
forming a patterned material layer on the third surface of the substrate, wherein the patterned material layer has an opening exposing the penetration via;
simultaneously filling a conductive layer into the penetration via and the opening such that the conductive layer in the penetration via becomes a TSV electrode and the conductive layer in the opening becomes a surface conductive layer; and
forming an integrated passive device (IPD) on the third surface, the IPD comprising a surface conductive layer, wherein the surface conductive layer is a redistribution layer disposed on the third surface, outside the penetration via, and the surface conductive layer and the TSV electrode are monolithic.