# US 9,437,490 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 9,437,490 B2
- Document ID: US9437490B2
- Status: Granted
- Kind: B2
- Application number: 14/230,775
- Filed: 2014-03-31
- Published: 2015-05-21
- Granted: 2016-09-06
- Earliest claimed: 2013-11-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Tsung-Yuan Yu; Hao-Yi Tsai; Chao-Wen Shih; Hung-Yi Kuo; Pi-Lan Chang
- Web page: https://patentgrep.com/patent/US9437490B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 72/90: Bond pads, in general
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a surface; and
a plurality of pads disposing on the surface of the substrate,
wherein the plurality of pads includes a first type pad and a second type pad, the first type pad is contacting a via located underlying the first type pad and within a projection area of the first type pad, and the second type pad is contacting an underlying isolation within a projection area of the second type pad, wherein the second type pad is laterally connected with a conductive trace, and the conductive trace connects to another via that is at a same level with the via, and the semiconductor device further comprises:
a conductive bump on the second type pad, wherein the conductive bump further connects to a conductive feature of a semiconductor die external to the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first type pad is arranged in a first region of the surface and the second type pad is arranged in a second region of the surface, and the second region is more proximal to a periphery of the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the via connects with a conductive trace underlying the first type pad.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the substrate includes a plurality of levels of conductive features and the via penetrates through the plurality of levels of conductive features.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second type pad is arranged proximal to a corner of the substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first type pad and the second type pad are arranged in an irregular array including a void region, and the void region has a lower pad density compared to other regions in the irregular array.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second type pad is arranged symmetrically to a geometric center of the pad array.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second type pad has a diameter substantially equal to a width of the conductive trace.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the conductive feature is in the substrate and at a level different from the second type pad.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the another via is connected to a conductive feature.