# US 9,437,487 B2 · Array substrate and fabrication method thereof, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,487 B2 - Document ID: US9437487B2 - Status: Granted - Kind: B2 - Application number: 14/574,721 - Filed: 2014-12-18 - Published: 2016-05-26 - Granted: 2016-09-06 - Earliest claimed: 2014-11-26 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Shi Shu; Feng Zhang; Yaohui Gu; Fang He; Feng Gu - Web page: https://patentgrep.com/patent/US9437487B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/133516: {Methods for their manufacture, e.g. printing, electro-deposition or photolithography} - G02F 1/13394: {spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence)} - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making} - G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/6723: {having light shields} - H10D 30/6737: {characterised by the electrode materials} - H10D 30/6743: {Silicon} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - G02F 1/136222: {Colour filters incorporated in the active matrix substrate} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 2201/121: common or background - G02F 2201/123: pixel - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer. ## Claims ### Claim 1 A fabrication method of an array substrate, the array substrate comprising gate lines and data lines intersecting with each other to define a plurality of pixel units, the method comprising: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer, wherein the via-hole conductive layer is provided at the via hole so that no portions of the via-hole conductive layer extent into a display region of each pixel unit. ### Claim 2 (depends on 1) The fabrication method of the array substrate according to claim 1, further comprising: forming a common electrode, wherein the via-hole conductive layer and the common electrode are formed simultaneously, and the via-hole conductive layer and the common electrode are disconnected from each other. ### Claim 3 (depends on 2) The fabrication method of the array substrate according to claim 2, further comprising: forming an inter-electrode insulating layer on the via-hole conductive layer and the common electrode; performing a patterning process on the inter-electrode insulating layer, so as to expose the via-hole conductive layer; and treating the via-hole conductive layer, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode. ### Claim 4 (depends on 3) The fabrication method of the array substrate according to claim 3, further comprising: forming the pixel electrode on the inter-electrode insulating layer. ### Claim 5 (depends on 1) The fabrication method of the array substrate according to claim 1, wherein the via-hole conductive layer is formed integrally with the pixel electrode. ### Claim 6 (depends on 5) The fabrication method of the array substrate according to claim 5, further comprising: forming a pixel electrode layer; coating a photoresist on the pixel electrode layer, exposing and developing the photoresist by using a dual-tone mask to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-removed region, the photoresist fully-reserved region corresponding to a region where the pixel electrode is to be formed, the photoresist partially-reserved region corresponding to a region where the via-hole conductive layer is to be formed, and the photoresist fully-removed region corresponding to other region; removing the pixel electrode layer in the photoresist fully-removed region by etching; removing the photoresist in the photoresist partially-reserved region by aching to form the via-hole conductive layer; treating the via-hole conductive layer with remaining photoresist as a mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode; and removing the remaining photoresist to obtain the pixel electrode. ### Claim 7 (depends on 5) The fabrication method of the array substrate according to claim 5, further comprising: forming a pixel electrode layer; performing a patterning process on the pixel electrode layer by using a first single-tone mask to form the pixel electrode and the via-hole conductive layer; and treating the via-hole conductive layer by using a second single-tone mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode. ### Claim 8 (depends on 1) The fabrication method of the array substrate according to claim 1, wherein the treating the via-hole conductive layer comprises: treating the via-hole conductive layer by a hydrogen treatment process. ### Claim 9 (depends on 8) The fabrication method of the array substrate according to claim 8, wherein hydrogen plasma is used in the hydrogen treatment process. ### Claim 10 (depends on 1) The fabrication method of the array substrate according to claim 1, further comprising: forming a black matrix and a color filter layer, wherein the black matrix is formed to correspond to the thin film transistor, and the color filter layer is formed to correspond to the pixel electrode. ### Claim 11 (depends on 1) The fabrication method of the array substrate according to claim 1, further comprising: forming an organic insulating layer, wherein the organic insulating layer is formed between a layer where the pixel electrode is provided and a layer where the drain electrode is provided. ### Claim 12 (depends on 1) The fabrication method of the array substrate according to claim 1, further comprising: forming a spacer, wherein the spacer is provided in a topmost layer of the array substrate. ### Claim 13 A fabrication method of an array substrate, comprising: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer, wherein the method further comprises: forming a pixel electrode layer; coating a photoresist on the pixel electrode layer, exposing and developing the photoresist by using a dual-tone mask to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-removed region, the photoresist fully-reserved region corresponding to a region where the pixel electrode is to be formed, the photoresist partially-reserved region corresponding to a region where the via-hole conductive layer is to be formed, and the photoresist fully-removed region corresponding to other region; removing the pixel electrode layer in the photoresist fully-removed region by etching; removing the photoresist in the photoresist partially-reserved region by ashing to form the via-hole conductive layer; treating the via-hole conductive layer with remaining photoresist as a mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode; and removing the remaining photoresist to obtain the pixel electrode. ### Claim 14 A fabrication method of an array substrate, comprising: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer, wherein the method further comprises: forming a pixel electrode layer; performing a patterning process on the pixel electrode layer by using a first single-tone mask to form the pixel electrode and the via-hole conductive layer; and treating the via-hole conductive layer by using a second single-tone mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode.