# US 9,437,480 B2 · Methods of forming semiconductor structures including tight pitch contacts and lines

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- Number: US 9,437,480 B2
- Document ID: US9437480B2
- Status: Granted
- Kind: B2
- Application number: 14/662,918
- Filed: 2015-03-19
- Published: 2015-07-09
- Granted: 2016-09-06
- Earliest claimed: 2007-08-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Luan C. Tran
- Web page: https://patentgrep.com/patent/US9437480B2

## CPC

- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/086: {involving buried masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

## Claims

### Claim 1

A method of fabricating a semiconductor structure, the method comprising:
forming a plurality of tight pitch trenches and a plurality of tight pitch contact holes in a single material removal process;
forming a plurality of tight pitch conductive lines and a plurality of tight pitch conductive contacts by introducing conductive material into each tight pitch trench of the plurality of tight pitch trenches and each tight pitch contact hole of the plurality of tight pitch contact holes.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the plurality of tight pitch trenches and the plurality of tight pitch contact holes in the single material removal process comprise etching through two or more material layers in a single, continuous etching process.

### Claim 3 (depends on 2)

The method of claim 2, further comprising composing at least one material of the two or more material layers to exhibit a variable etch rate, through a thickness of the at least one material, with respect to an etchant.

### Claim 4 (depends on 1)

The method of claim 1, wherein etching through the two or more material layers in a single, continuous etching process comprises:
etching through at least one material layer of the two or more material layers to form the plurality of tight pitch trenches in the at least one material layer; and
etching through at least another material layer of the two or more material layers to form the plurality of tight pitch contact holes in the at least another material layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the plurality of tight pitch trenches are not disposed in the at least another material layer.

### Claim 6 (depends on 4)

The method of claim 4, wherein etching through at least another material layer of the two or more material layers to form the plurality of tight pitch contact holes comprises etching through an aperture in a mask.

### Claim 7 (depends on 6)

The method of claim 6, wherein etching through the aperture in the mask comprises etching through a dielectric material disposed within the aperture in the mask.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming the plurality of tight pitch contact holes to extend through the dielectric material and through the aperture in the mask.

### Claim 9 (depends on 6)

The method of claim 6, wherein etching through the aperture in the mask comprises etching through an aperture in a hard mask.

### Claim 10 (depends on 1)

The method of claim 1, wherein introducing conductive material into each tight pitch trench of the plurality of tight pitch trenches and each tight pitch contact hole of the plurality of tight pitch contact holes comprises filling at least a portion of each tight pitch trench of the plurality of tight pitch trenches and at least a portion of each tight pitch contact hole of the plurality of tight pitch contact holes with conductive material in a single, continuous process.

### Claim 11 (depends on 10)

The method of claim 10, further comprising integrally forming each tight pitch conductive contact of the plurality of tight pitch conductive contacts with a respective tight pitch conductive line of the plurality of tight pitch conductive lines.

### Claim 12 (depends on 1)

The method of claim 1, further comprising forming a plurality of tight pitch spacers, and using the tight pitch spacers as mask structures while forming the plurality of tight pitch trenches and the plurality of tight pitch contact holes in the single material removal process.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the plurality of tight pitch spacers comprises at least one of a pitch multiplication process, a double-patterning process, a double exposure process, a maskless photolithography process, and an advanced fine line lithography process.

### Claim 14

A method of forming a semiconductor device, comprising:
forming a first volume of material over tight pitch features on a substrate;
forming a mask having an aperture over the first volume of material;
forming a second volume of material over the mask;
in a single continuous etching process, etching through the second volume of material to form tight pitch trenches in the second volume of material, and etching through the aperture in the mask and through the first volume of material to form tight pitch contact holes extending through the aperture in the mask and through the first volume of material to the tight pitch features; and
filling the tight pitch contact holes and tight pitch trenches with conductive material to form tight pitch conductive contacts and tight pitch conductive lines, each tight pitch conductive contact electrically contacting a respective feature of the tight pitch features on the substrate and integrally formed with a respective tight pitch conductive line of the tight pitch conductive lines.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming tight pitch spacers over the second volume of material and using the tight pitch spacers as mask structures during the single continuous etching process.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming tight pitch spacers over the second volume of material comprises at least one of a pitch multiplication process, a double-patterning process, a double exposure process, a maskless photolithography process, and an advanced fine line lithography process.

### Claim 17 (depends on 14)

The method of claim 14, wherein the tight pitch trenches are not disposed in the first volume of material.

### Claim 18 (depends on 14)

The method of claim 14, further comprising forming the first volume of material and the second volume of material to have at least substantially the same composition.

### Claim 19 (depends on 14)

The method of claim 14, wherein filling the tight pitch contact holes and tight pitch trenches with conductive material to form tight pitch conductive contacts and tight pitch conductive lines comprises filling at least a portion of each tight pitch trench and at least a portion of each tight pitch contact hole with conductive material in a single, continuous process.

### Claim 20 (depends on 14)

The method of claim 14, wherein the tight pitch features are selected from group consisting of transistor sources regions, transistor drain regions, and transistor gate regions.