# US 9,437,478 B2 · Chip package and method for forming the same

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- Number: US 9,437,478 B2
- Document ID: US9437478B2
- Status: Granted
- Kind: B2
- Application number: 14/339,360
- Filed: 2014-07-23
- Published: 2014-11-13
- Granted: 2016-09-06
- Earliest claimed: 2010-05-11
- Assignees: Xintec Inc.
- Applicants: Xintec Inc.
- Inventors: Yen-Shih Ho; Tsang-Yu Liu; Shu-Ming Chang; Yu-Lung Huang; Chao-Yen Lin; Wei-Luen Suen; Chien-Hui Chen; Ho-Yin Yiu
- Web page: https://patentgrep.com/patent/US9437478B2

## CPC

- H10W 20/081: {by forming openings in the dielectric parts}
- G06V 40/1329: {Protecting the fingerprint sensor against damage caused by the finger}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 20/48: Insulating materials thereof
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/652: Cross-sectional shapes
- H10W 70/69: Insulating materials thereof
- H10W 72/01515: {Forming coatings}
- H10W 72/0198: {batch processes}
- H10W 72/075: {of bond wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

## Claims

### Claim 1

A chip package, comprising:
a chip including a semiconductor substrate, comprising:
a sensing region or device region adjacent to an upper surface of the chip; and
a sensing array in the sensing region or device region and comprising a plurality of sensing units that measure changes to external physical quantities;
a plurality of first openings in the chip and correspondingly exposing the plurality of sensing units; and
a plurality of conductive extending portions disposed in the plurality of first openings and electrically connected to the plurality of sensing units, wherein the plurality of conductive extending portions extends from the plurality of first openings onto the upper surface of the chip.

### Claim 2 (depends on 1)

The chip package as claimed in claim 1, wherein the chip is a fingerprint-recognition chip.

### Claim 3 (depends on 1)

The chip package as claimed in claim 1, wherein the chip further comprises a signal pad region adjacent to the upper surface and outside of the sensing region or device region, and wherein the chip package further comprises:
a second opening in the chip and exposing the signal pad region;
a shallow recess structure outside of the signal pad region and extending from the upper surface toward a lower surface of the chip; and
a redistribution layer electrically connected to the signal pad region through the second opening and extending into the shallow recess structure.

### Claim 4 (depends on 3)

The chip package as claimed in claim 3, wherein the plurality of conductive extending portions and the redistribution layers are formed of a same material layer.

### Claim 5 (depends on 3)

The chip package as claimed in claim 3, further comprises a wire having a first end and a second end, wherein the first end is disposed in the shallow recess structure and electrically connected to the redistribution layer, and the second end is used for external electrical connection.

### Claim 6 (depends on 5)

The chip package as claimed in claim 5, wherein a highest portion of the wire is lower than the upper surface of the chip.

### Claim 7 (depends on 5)

The chip package as claimed in claim 5, wherein the first end and the second end of the wire are lower than the upper surface of the chip, and a highest portion of the wire protrudes from the upper surface of the chip.

### Claim 8 (depends on 7)

The chip package as claimed in claim 7, further comprising an encapsulant layer covering the wire and the upper surface to form a flat contacting region above the sensing region or device region, wherein a thickness of the encapsulant layer covering the sensing region or device region is determined by a difference between a distance from the highest portion of the wire to a bottom of the shallow recess structure and a depth of the shallow recess structure.

### Claim 9 (depends on 3)

The chip package as claimed in claim 3, wherein the shallow recess structure has at least a first recess and a second recess under the first recess, and wherein the redistribution layer extends to a first sidewall and a first bottom of the first recess.

### Claim 10 (depends on 9)

The chip package as claimed in claim 9, wherein the second recess extends from the first bottom of the first recess toward the lower surface of the chip.

### Claim 11 (depends on 9)

The chip package as claimed in claim 9, wherein the redistribution layer further extends to a second sidewall and a second bottom of the second recess.

### Claim 12 (depends on 9)

The chip package as claimed in claim 9, wherein the chip comprises a substrate and an insulating layer, and wherein the first sidewall of the first recess adjoins the insulating layer and a portion of the substrate and a second sidewall of the second recess adjoins the substrate.

### Claim 13

A method for forming a chip package, comprising:
providing a chip including a semiconductor substrate, wherein the chip comprises:
a sensing region or device region adjacent to an upper surface of the chip; and
a sensing array in the sensing region or device region and comprising a plurality of sensing units that measure changes to external physical quantities;
forming a plurality of first openings in the chip to correspondingly expose the plurality of sensing units; and
forming a plurality of conductive extending portions in the plurality of first openings to electrically connect to the plurality of sensing units, wherein the plurality of conductive extending portions extends from the plurality of first openings onto the upper surface of the chip.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the chip is a fingerprint-recognition chip.

### Claim 15 (depends on 13)

The method as claimed in claim 13, wherein the chip further comprises a signal pad region adjacent to the upper surface and outside of the sensing region or device region, and wherein the step of forming the plurality of first openings further comprises forming a second opening in the chip to expose the signal pad region.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the step of forming the plurality of conductive extending portions comprises:
forming a conducting layer on the upper surface of the chip and extending into the plurality of first openings; and
patterning the conducting layer to form the plurality of conductive extending portions.

### Claim 17 (depends on 16)

The method as claimed in claim 16, further comprising forming a shallow recess structure outside of the signal pad region and extending from the upper surface toward a lower surface of the chip, wherein the conducting layer further extends into the second opening and the shallow recess structure.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein the step of patterning the conducting layer further comprises forming a redistribution layer electrically connected to the signal pad region through the second opening and extending into the shallow recess structure.

### Claim 19 (depends on 18)

The method as claimed in claim 18, further comprising bonding a wire having a first end and a second end to the chip, wherein the first end is formed in the shallow recess structure and is electrically connected to the redistribution layer, the second end is used for external electrical connection.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein the second end of the wire is an initial end for wire bonding.

### Claim 21 (depends on 19)

The method as claimed in claim 19, wherein a highest portion of the wire is lower than the upper surface of the chip.

### Claim 22 (depends on 19)

The method as claimed in claim 19, wherein the first end and the second end of the wire are lower than the upper surface of the chip, and a highest portion of the wire protrudes from the upper surface of the chip.

### Claim 23 (depends on 22)

The method as claimed in claim 22, further comprising covering the wire and the upper surface by an encapsulant layer to form a flat contacting region above the sensing region or device region, wherein a thickness of the encapsulant layer covering the sensing region or device region is determined by a difference between a distance from the highest portion of the wire to a bottom of the shallow recess structure and a depth of the shallow recess structure.

### Claim 24 (depends on 18)

The method as claimed in claim 18, wherein the shallow recess structure has at least a first recess and a second recess under the first recess, and wherein the redistribution layer extends to a first sidewall and a first bottom of the first recess.

### Claim 25 (depends on 24)

The method as claimed in claim 24, wherein the second recess extends from the first bottom of the first recess toward the lower surface of the chip.

### Claim 26 (depends on 24)

The method as claimed in claim 24, wherein the redistribution layer further extends to a second sidewall and a second bottom of the second recess.

### Claim 27 (depends on 24)

The method as claimed in claim 24, wherein the chip comprises a substrate and an insulating layer, and wherein the first sidewall of the first recess adjoins the insulating layer and a portion of the substrate and a second sidewall of the second recess adjoins the substrate.