# US 9,437,474 B2 · Method for fabricating microelectronic devices with isolation trenches partially formed under active regions

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- Number: US 9,437,474 B2
- Document ID: US9437474B2
- Status: Granted
- Kind: B2
- Application number: 14/425,891
- Filed: 2012-09-05
- Published: 2015-10-15
- Granted: 2016-09-06
- Earliest claimed: 2012-09-05
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternative
- Applicants: Laurent Grenouillet; Yannick Le Tiec; Nicolas Loubet; Maud Vinet; Romain Wacquez
- Inventors: Laurent Grenouillet; Yannick Le Tiec; Nicolas Loubet; Maud Vinet; Romain Wacquez
- Web page: https://patentgrep.com/patent/US9437474B2

## CPC

- H10P 90/1906: {Preparing SOI wafers}
- H10D 86/01: Manufacture or treatment
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

## Claims

### Claim 1

A method of producing a microelectronic device in a substrate comprising a first semiconductor layer disposed on a dielectric layer, the dielectric layer being disposed on a second semiconductor layer, the method comprising:
etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer such that another part of the thickness of the second semiconductor layer remains under a bottom wall of the trench, thus defining, in the first semiconductor layer, at least one active region of the microelectronic device;
performing ionic implantation in one or more side walls of the trench, at a level of the second semiconductor layer, modifying the crystallographic properties, or the chemical properties, or both the crystallographic properties and the chemical properties, of the implanted second semiconductor layer in said side walls;
etching the implanted second semiconductor layer such that at least a part of the trench extends under a part of the active region; and
filling the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under the part of the active region.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the portions of the isolation trench that extend under the part of the active region are in contact with a portion of the dielectric layer disposed under the active region.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the semiconductor of the second semiconductor layer is crystalline, and the ionic implantation in said one or more side walls of the trench is such that the implanted second semiconductor layer becomes amorphous.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the ionic implantation in said one or more side walls of the trench is such that the implanted second semiconductor layer becomes a compound of said semiconductor and of an implanted ionic species.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the etching of the implanted second semiconductor layer is made using HCl as etching agent.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the ionic implantation is carried out with at least one ion beam having an energy of between about 0.5 keV and 40 keV, and/or a dose between about 5.1013 and 5.1016 at.cm−2, and/or oriented such that an angle between said one or more side walls of the trench and the ion beam is between around 5° and 20°.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the ionic implantation is also performed in the bottom wall of the trench.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising, between the step of etching the trench and the step of ionic implantation, a step of producing at least one dielectric layer forming side walls of the isolation trench against the dielectric layer and the first semiconductor layer.

### Claim 9 (depends on 1)

The method according to claim 1,
wherein the active region is substantially rectangular in shape and bounded by at least four side walls of the isolation trench extending through the first semiconductor layer, the dielectric layer and said part of the thickness of the second semiconductor layer, and
wherein, at the level of said part of the thickness of the second semiconductor layer, two of the four side walls which are substantially parallel with respect to each other extend under a part of the active region and the two other side walls do not extend under the active region.

### Claim 10 (depends on 1)

The method according to claim 1,
wherein the active region is substantially rectangular in shape and bounded by side walls of the isolation trench extending through the first semiconductor layer, the dielectric layer and said part of the thickness of the second semiconductor layer, and
wherein, at the level of said part of the thickness of the second semiconductor layer, the side walls extend under a part of the active region.

### Claim 11 (depends on 9)

The method according to claim 9, further comprising, after the step of filling of the trench, a step of producing at least one transistor in the active region, the transistor comprising a gate made on a part of the active region and on a part of said two other side walls.

### Claim 12 (depends on 1)

The method according to claim 1, further comprising, after the step of filling of the trench, a step of producing at least one transistor in the active region, the transistor comprising a gate made on a part of the active region.