# US 9,437,472 B2 · Semiconductor line feature and manufacturing method thereof

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- Number: US 9,437,472 B2
- Document ID: US9437472B2
- Status: Granted
- Kind: B2
- Application number: 14/192,439
- Filed: 2014-02-27
- Published: 2015-08-27
- Granted: 2016-09-06
- Earliest claimed: 2014-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Wen-Han Fang; Po-Chi Wu
- Web page: https://patentgrep.com/patent/US9437472B2

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H01J 37/321: {the radio frequency energy being inductively coupled to the plasma}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)

## Abstract

Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.

## Claims

### Claim 1

A manufacturing method for a semiconductor isolation structure, comprising:
patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a substrate by performing a first plasma etch at a first temperature;
forming a trench having a sidewall angle greater than 88 degrees in the substrate correlated to the line feature by performing a second plasma etch at a second temperature;
rounding a bottom of the trench by performing a third plasma etch at the second temperature; and
filling the trench with isolation materials,
wherein the first plasma etch is performed with at least two different plasma densities along a radial direction of the hard mask simultaneously, and the second plasma etch is performed with a uniform plasma density along the radial direction of the hard mask, and
wherein the at least two different plasma densities are formed by applying a current ratio in a range of from about 0.5 to about 0.8 between the current entering a first set of magnetic coils close to a center of the wafer and the current entering a second set of the magnetic coils close to an edge of the wafer.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein the patterning a hard mask comprises controlling the amount of current passing through an electrostatic chuck supporting the substrate to maintain the first temperature.

### Claim 3 (depends on 2)

The manufacturing method of claim 2, wherein the first temperature is controlled to be within a range of from about 40 to about 60 degrees Celsius.

### Claim 4 (depends on 1)

The manufacturing method of claim 1, wherein the forming a trench in the substrate and rounding the bottom of the trench comprises controlling the amount of current passing through an electrostatic chuck supporting the substrate to maintain the second temperature.

### Claim 5 (depends on 4)

The manufacturing method of claim 4, wherein the second temperature is controlled to be within a range of from about 50 to about 80 degrees Celsius.

### Claim 6 (depends on 1)

The manufacturing method of claim 1, wherein the patterning a hard mask exposing a line feature comprises introducing fluorine-containing gas, oxygen gas, and nitrogen gas into an etching chamber.

### Claim 7

A method for controlling a semiconductor line feature in a wafer, comprising:
patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer by performing a first plasma etch, comprising:
forming at least two different temperature zones across the wafer, comprising forming concentric-distributed temperature zones with a higher temperature zone close to an edge of the wafer and a lower temperature zone close to a center of the wafer, and the higher temperature zone being three degrees Celsius greater than the lower temperature zone; and
forming at least two different plasma density zones over the wafer by applying a current ratio lower than 0.8 between the current entering a first set of magnetic coils close to the center of the wafer and the current entering a second set of the magnetic coils close to the edge of the wafer;
forming a trench having a sidewall angel greater than 88 degrees in the wafer correlated to the line feature by performing a second plasma etch over the wafer; and
filling the trench with isolation materials.

### Claim 8 (depends on 7)

The method for controlling a semiconductor line feature in a wafer of claim 7, wherein the forming concentric-distributed temperature zones comprises passing different amount of current through different temperature zones.

### Claim 9 (depends on 7)

The method for controlling a semiconductor line feature in a wafer of claim 7, wherein the forming at least two different plasma density zones over the wafer comprises forming concentric-distributed plasma density zones with a higher plasma density close to the edge of the wafer and a lower plasma density close to the center of the wafer.

### Claim 10 (depends on 9)

The method for controlling a semiconductor line feature in a wafer of claim 9, wherein the forming at least two different plasma density zones over the wafer comprises applying a current ratio between the current entering the magnetic coils close to the center of the wafer and the current entering the magnetic coils close to the edge of the wafer to be in a range of from about 0.5 to about 0.8.

### Claim 11 (depends on 7)

The method for controlling a semiconductor line feature in a wafer of claim 7, further comprising performing a rounding operation at the bottom of the trench under a uniform temperature across different temperature zones.

### Claim 12 (depends on 11)

The method for controlling a semiconductor line feature in a wafer of claim 11, wherein the uniform temperature is in a range of from about 50 to about 80 degrees Celsius.

### Claim 13 (depends on 7)

The method for controlling a semiconductor line feature in a wafer of claim 7, wherein the performing the first plasma etch over the wafer comprises introducing fluorine-containing gas, oxygen gas, and nitrogen gas into an etching chamber.

### Claim 14 (depends on 7)

The method for controlling a semiconductor line feature in a wafer of claim 7, wherein the performing the second plasma etch over the wafer comprises introducing hydrogen halide gas, oxygen gas, and nitrogen gas into an etching chamber.

### Claim 15

A manufacturing method for a semiconductor isolation structure, comprising:
patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer by performing a first plasma etch, comprising:
forming at least two different temperature zones across the wafer, comprising forming concentric-distributed temperature zones with a higher temperature zone close to an edge of the wafer and a lower temperature zone close to a center of the wafer, and the higher temperature zone being three degrees Celsius greater than the lower temperature zone; and
forming at least two different plasma density zones over the wafer by applying a current ratio lower than 0.8 between the current entering a first set of magnetic coils close to the center of the wafer and the current entering a second set of the magnetic coils close to the edge of the wafer;
forming a trench having a sidewall angle greater than 88 degrees in the wafer correlated to the line feature by performing a second plasma etch over the wafer; and
rounding a bottom of the trench by performing a third plasma etch.

### Claim 16 (depends on 15)

The manufacturing method of claim 15, wherein the forming at least two different plasma density zones over the wafer comprises controlling a current ratio in a range of from about 0.5 to about 0.8, wherein the first set and second set of the magnetic coils are electromagnetic coils.

### Claim 17 (depends on 15)

The manufacturing method of claim 15, wherein the forming at least two different temperature zones across the wafer comprises flowing a fluid into an electrostatic chuck (ESC) supporting the wafer, passing desired amount of current into or around the ESC, or a combination thereof.

### Claim 18 (depends on 15)

The manufacturing method of claim 15, wherein the second plasma etch is a time-controlled process.