# US 9,437,470 B2 · Self-aligned trench isolation in integrated circuits

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- Number: US 9,437,470 B2
- Document ID: US9437470B2
- Status: Granted
- Kind: B2
- Application number: 14/048,863
- Filed: 2013-10-08
- Published: 2015-04-09
- Granted: 2016-09-06
- Earliest claimed: 2013-10-08
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Ching-Huang Lu; Lei Xue; Kenichi Ohtsuka; Simon Siu-Sing Chan; Rinji Sugino
- Web page: https://patentgrep.com/patent/US9437470B2

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10B 41/30: characterised by the memory core region
- H10B 43/30: characterised by the memory core region
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

## Claims

### Claim 1

An integrated circuit (IC) comprising:
a substrate;
first and second devices having:
respective first and second gate structures,
respective first and second doped regions; and
a trench in the substrate self-aligned between the first and second gate structures, the trench comprising:
a first filled portion comprising a dielectric material configured to form a buried trench isolation between the first and second devices; and
a second filled portion comprising a conductive material, wherein a top surface of the second filled portion is substantially coplanar with a top surface of the substrate,
wherein the first and second doped regions are substantially in contact with at least a part of the second filled portion.

### Claim 2 (depends on 1)

The IC of claim 1, wherein a top surface of the first filled portion is substantially in contact with a bottom surface of the second filled portion.

### Claim 3 (depends on 1)

The IC of claim 1, wherein at least one of the first and second gate structures comprises:
a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on the top surface of the substrate; and
a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the dielectric layer.

### Claim 4 (depends on 1)

The IC of claim 1, wherein at least one of the first and second gate structures comprises:
a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on the top surface of the substrate; and
a first and second gate layer, each of the first and second gate layers comprising a polycrystalline silicon layer or a metal layer.

### Claim 5 (depends on 4)

The IC of claim 4, wherein:
the first gate layer is disposed on the dielectric layer; and
the second gate layer is disposed on the first gate layer.

### Claim 6 (depends on 1)

The IC of claim 1, wherein at least one of the first and second gate structures comprises:
a charge storing layer disposed between a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on the top surface of the substrate; and
a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the second dielectric layer.

### Claim 7 (depends on 6)

The IC of claim 6, wherein:
the charge storing layer comprises a nitride layer or a polycrystalline silicon layer; and
each of the first and second dielectric layers comprises an oxide layer.

### Claim 8

An integrated circuit (IC) comprising:
a substrate;
first and second devices each having a doped region; and
a trench in the substrate self-aligned between the first and second devices, the trench comprising:
a first filled portion comprising a dielectric material configured to electrically isolate the first and second devices; and
a second filled portion comprising a conductive material,
wherein the doped regions are substantially in contact with at least a part of the second filled portion.

### Claim 9 (depends on 8)

The IC of claim 8, wherein a top surface of the first filled portion is substantially in contact with a bottom surface of the second filled portion.

### Claim 10 (depends on 8)

The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:
a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on a top surface of the substrate; and
a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the dielectric layer.

### Claim 11 (depends on 8)

The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:
a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on a top surface of the substrate; and
a first and second gate layer, each of the first and second gate layers comprising a polycrystalline silicon layer or a metal layer.

### Claim 12 (depends on 11)

The IC of claim 11, wherein:
the first gate layer is disposed on the dielectric layer; and
the second gate layer is disposed on the first gate layer.

### Claim 13 (depends on 8)

The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:
a charge storing layer disposed between a first dielectric layer and a second dielectric Layer, the first dielectric layer being disposed on a top surface of the substrate; and
a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the second dielectric layer.

### Claim 14 (depends on 13)

The IC of claim 13, wherein:
the charge storing layer comprises a nitride layer or a polycrystalline silicon layer: and
each of the first and second dielectric layers comprises an oxide layer.