# US 9,437,454 B2 · Wiring board, semiconductor device, and manufacturing methods thereof

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- Number: US 9,437,454 B2
- Document ID: US9437454B2
- Status: Granted
- Kind: B2
- Application number: 13/161,871
- Filed: 2011-06-16
- Published: 2011-12-29
- Granted: 2016-09-06
- Earliest claimed: 2010-06-29
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Motomu Kurata; Shinya Sasagawa; Fumika Taguchi; Yoshinori Ieda
- Inventors: Motomu Kurata; Shinya Sasagawa; Fumika Taguchi; Yoshinori Ieda
- Web page: https://patentgrep.com/patent/US9437454B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/266: {by vapour etching only}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 70/095: {of vias therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

## Claims

### Claim 1

A semiconductor device comprising:
a gate electrode layer of a first transistor;
an insulating layer covering a side surface of the gate electrode layer; and
a source or a drain electrode layer of a second transistor over and in contact with the insulating layer and with a portion of the gate electrode layer protruded from the insulating layer,
wherein a surface of the portion of the gate electrode layer protruded from the insulating layer is curved, and
wherein a surface of another portion of the gate electrode layer protruded from the insulating layer is curved, and the another portion of the gate electrode layer does not touch the source or the drain electrode layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a line width of the gate electrode layer is 1 μm or less.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device is incorporated in one selected from the group consisting of a laptop personal computer, a portable information terminal, an e-book reader, a mobile phone, and a digital camera.

### Claim 4

A semiconductor device comprising:
a gate electrode layer of a first transistor;
a first insulating layer covering a side surface of the gate electrode layer;
a second insulating layer over the first insulating layer; and
a source or a drain electrode layer of a second transistor over and in contact with the second insulating layer and with a portion of the gate electrode layer protruded from the first insulating layer and the second insulating layer,
wherein a surface of the portion of the gate electrode layer protruded from the first insulating layer and the second insulating layer is curved, and
wherein a surface of another portion of the gate electrode layer protruded from the first insulating layer and the second insulating layer is curved, and the another portion of the gate electrode layer does not touch the source or the drain electrode layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein a line width of the gate electrode layer is 1 μm or less.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the semiconductor device is incorporated in one selected from the group consisting of a laptop personal computer, a portable information terminal, an e-book reader, a mobile phone, and a digital camera.