# US 9,437,445 B1 · Dual fin integration for electron and hole mobility enhancement

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- Number: US 9,437,445 B1
- Document ID: US9437445B1
- Status: Granted
- Kind: B1
- Application number: 14/630,072
- Filed: 2015-02-24
- Published: 2016-08-25
- Granted: 2016-09-06
- Earliest claimed: 2015-02-24
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chia-Yu Chen; Zuoguang Liu; Miaomiao Wang; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US9437445B1

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a plurality of sacrificial mandrels over a hardmask layer, the hardmask layer disposed over a semiconductor layer;
forming a plurality of spacers on sidewalls of the plurality of sacrificial mandrels;
removing the plurality of sacrificial mandrels to leave the plurality of spacers;
performing a masking process to leave exposed a first set of the plurality of spacers with a second set of the plurality of spacers protected;
in response to the masking process, performing a first fin etch process to form a first set of fins in the semiconductor layer using the first set of the plurality of spacers, wherein the first set of fins has a vertical sidewall profile, wherein the first set of fins comprises positive channel field effect transistors (PFET) devices;
performing another masking process to leave exposed the second set of the plurality of spacers with the first set of the plurality of spacers and the first set of fins protected;
in response to the another masking process, performing a second fin etch process to form a second set of fins in the semiconductor layer using the second set of the plurality of spacers, wherein the second set of fins has a trapezoidal sidewall profile.

### Claim 2 (depends on 1)

The method of claim 1, wherein during the masking process a first mask covers the second set of the plurality of spacers.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first mask is an oxide.

### Claim 4 (depends on 1)

The method of claim 1, wherein during the another masking process a second mask covers the first set of the plurality of spacers.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second mask is an oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plurality of spacers include at least one of an oxide and a nitride.

### Claim 7 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises at least one of silicon and germanium.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second set of fins comprises negative channel field effect transistors (NFET) devices.

### Claim 9 (depends on 1)

The method of claim 1, wherein a gate electrode is formed over the first set of fins and the second set of fins.

### Claim 10 (depends on 1)

The method of claim 1, wherein a base width of the second set of fins is at least twice a length of a top width of the second set of fins.

### Claim 11 (depends on 1)

The method of claim 1, wherein a height of the second set of fins is about equal to a height of the first set of fins.

### Claim 12 (depends on 1)

The method of claim 1, wherein an integrated circuit includes the first set of fins and the second set of fins.

### Claim 13 (depends on 12)

The method of claim 12, wherein an individual microprocessor includes the integrated circuit having the first set of fins and the second set of fins, such that the first set of fins comprises PFET devices and the second set of fins comprises NFET devices.