# US 9,437,441 B2 · Methods for etching substrate and semiconductor devices

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- Number: US 9,437,441 B2
- Document ID: US9437441B2
- Status: Granted
- Kind: B2
- Application number: 14/835,513
- Filed: 2015-08-25
- Published: 2016-05-12
- Granted: 2016-09-06
- Earliest claimed: 2014-11-11
- Assignees: Industry-Academic Cooperation Foundation, Yonsei University
- Applicants: Industry-Academic Cooperation Foundation, Yonsei University
- Inventors: Jungwoo Oh; Yunwon Song; Bugeun Ki; Keorock Choi
- Web page: https://patentgrep.com/patent/US9437441B2

## CPC

- H10P 50/648: {Anisotropic liquid etching}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of etching a substrate using a metal-assisted chemical etching process is provided. The method may include forming a metal catalytic layer to a predetermined thickness on a substrate and reacting the metal catalytic layer with the etching solution to form a porous surface in the metal catalytic layer and etch the substrate. When the metal catalytic layer is reacted with an etching solution, a porous surface may be formed on the metal catalytic layer.

## Claims

### Claim 1

A method of etching a substrate using a metal-assisted chemical etching process, the method comprising:
forming a metal catalytic layer to have a thickness greater than 3 nm and less than 10 nm on a substrate; and
reacting the metal catalytic layer with the etching solution to form a porous surface in the metal catalytic layer and etch the substrate,
wherein a plurality of pin holes of the porous surface are formed in the metal catalytic layer, the plurality of pin holes being formed by the reaction with the etching solution, and
wherein the pin holes are formed in the metal catalytic layer to have a density of 1-300 ea/μm2.

### Claim 2 (depends on 1)

The method of claim 1, wherein the metal catalytic layer comprises at least one metal catalytic material selected from Au, Ag, Pt, and Pd.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metal catalytic layer on the substrate is formed to have a thickness ranging from 4 nm to 6 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the etching solution contains at least one selected from H2SO4 and HF and at least one selected from KMnO4 and H2O2.

### Claim 5 (depends on 4)

The method of claim 4, wherein the etching solution contains H2SO4 and KMnO4, and a molar concentration ratio of H2SO4 to KMnO4 ranges from 200:1 to 1000:1.

### Claim 6 (depends on 5)

The method of claim 5, wherein a temperature of the etching solution ranges from 40° C. to 60° C.

### Claim 7

A semiconductor device, comprising:
a substrate; and
a metal catalytic layer on the substrate, the metal catalytic layer being provided to have a thickness greater than 3 nm and less than 10 nm, the metal catalytic layer having a porous surface,
wherein a plurality of pin holes of the porous surface are formed in the metal catalytic layer, the plurality of pin holes being formed by the reaction with the etching solution to have a density of 1-300 ea/μm2.

### Claim 8 (depends on 7)

The device of claim 7, wherein the substrate is a compound semiconductor substrate comprising at least one selected from gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN).

### Claim 9 (depends on 7)

The device of claim 7, wherein the metal catalytic layer comprises at least one metal catalytic material selected from Au, Ag, Pt, and Pd.