# US 9,437,436 B2 · Replacement metal gate FinFET

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- Number: US 9,437,436 B2
- Document ID: US9437436B2
- Status: Granted
- Kind: B2
- Application number: 14/609,803
- Filed: 2015-01-30
- Published: 2015-05-21
- Granted: 2016-09-06
- Earliest claimed: 2012-10-24
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Hemanth Jagannathan; Sanjay C. Mehta; Junli Wang; Chun-Chen Yeh; Stefan Schmitz
- Web page: https://patentgrep.com/patent/US9437436B2

## CPC

- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

## Claims

### Claim 1

A field effect transistor (FET) device, comprising:
a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region;
a hardmask layer disposed on the top surface of the fin, over the channel region;
a gate stack formed on the hardmask layer, the gate stack comprising a gate dielectric material having a U-shape that is arranged along sidewalls and a bottom surface of the gate stack; and
sidewall spacers adjacent sidewalls of the gate stack, wherein bottom surfaces of the sidewall spacers are formed over the hardmask layer, and portions of the gate dielectric material are arranged between the sidewall spacers and the hardmask layer.

### Claim 2 (depends on 1)

The FET device of claim 1, wherein the gate stack comprises one or more of a dielectric layer, a work function metal layer, and a metallic gate material.

### Claim 3 (depends on 1)

The FET device of claim 1, wherein the hardmask layer includes an oxide material.

### Claim 4 (depends on 1)

The FET device of claim 1, wherein the sidewall spacers comprise one of an oxide material and a nitride material.

### Claim 5 (depends on 1)

The FET device of claim 1, wherein the hardmask layer comprises an oxide material.