# US 9,437,435 B2 · LTPS TFT having dual gate structure and method for forming LTPS TFT

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- Number: US 9,437,435 B2
- Document ID: US9437435B2
- Status: Granted
- Kind: B2
- Application number: 14/415,607
- Filed: 2014-11-14
- Published: 2016-05-12
- Granted: 2016-09-06
- Earliest claimed: 2014-11-11
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd
- Inventors: Xiaoxiao Wang; Hsiang Chih Hsiao; Peng Du; Chang-I Su; Hongyuan Xu; Bo Sun
- Web page: https://patentgrep.com/patent/US9437435B2

## CPC

- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

## Claims

### Claim 1

A method for forming an LTPS TFT having a dual-gate structure, comprising:
forming a plurality of patterned a-Si layers disposed on a substrate;
forming a barrier layer on the plurality of patterned a-Si layers;
forming a first patterned poly-Si layer and a second patterned poly-Si layer on the barrier layer;
coating a first photoresist layer on a top surface of the second patterned poly-Si layer and surrounding the second patterned poly-Si layer;
forming an N-type channel by doping the first patterned poly-Si layer;
removing the first photoresist layer from the second patterned poly-Si layer;
forming a gate insulation layer on both of the second patterned poly-Si layer and the first patterned poly-Si layer where the N-type channel is formed;
forming a second photoresist layer on the gate insulation layer, and doping the second patterned poly-Si layer to form a P+-type layer;
removing the second photoresist layer from the gate insulation layer, and coating a third photoresist layer on the gate insulation layer;
removing a part of the third photoresist layer, a part of the gate insulation layer, and a part of the barrier layer by performing exposing and developing processes, for forming a plurality of openings;
N+doping a part of the patterned a-Si layer and a part of the first patterned poly-Si layer which are not covered by the gate insulation layer;
forming a plurality of patterned GE layers on the gate insulation layer;
N−doping the first patterned poly-Si layer and the second patterned poly-Si layer with the plurality of patterned GE layers as a second shielding layer, the plurality of patterned GE layers corresponding to the first patterned poly-Si layer connected to and conducted to the N+-type layer of the patterned a-Si layer, and the plurality of patterned GE layers and the N+-type layer forming a dual-gate structure;
forming an ILD on the plurality of patterned GE layers and the gate insulation layer;
forming a plurality of via holes penetrating the ILD and the gate insulation layer; and
forming a plurality of patterned source/drain electrodes through the plurality of via holes, the plurality of patterned source/drain electrodes connected to the P+-type layer which is connected to the second patterned poly-Si layer to for a PMOS, and the plurality of patterned source/drain electrodes connected to the N+-type layer which is connected to the first patterned poly-Si layer to form an NMOS.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the N+-type layer is doped with the exposed part of the patterned a-Si layer for forming an ohmic contact with a metallic electrode.