# US 9,437,427 B1 · Controlled confined lateral III-V epitaxy

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- Number: US 9,437,427 B1
- Document ID: US9437427B1
- Status: Granted
- Kind: B1
- Application number: 14/984,546
- Filed: 2015-12-30
- Granted: 2016-09-06
- Earliest claimed: 2015-12-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karthik Balakrishnan; Lukas Czornomaz; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9437427B1

## CPC

- H10P 14/274: {using seed materials}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/3466: {Crystal orientation}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 36/00: Gettering within semiconductor bodies
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/646: {of Group III-V materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

After oxidizing a sacrificial semiconductor layer composed of silicon germanium that is located over an insulator layer to form a germanium-enriched region located within a first end of the sacrificial semiconductor layer and having a greater germanium concentration than a remaining portion of the sacrificial semiconductor layer, the remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the germanium-enriched region that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming dielectric material layer over a sacrificial semiconductor layer that is located over a region of an insulator layer, wherein the sacrificial semiconductor layer comprises silicon-germanium having a first germanium concentration;
forming a first trench opening extending through the dielectric material layer and the sacrificial semiconductor layer, wherein the first trench opening exposes a first sidewall of the sacrificial semiconductor layer;
oxidizing the sacrificial semiconductor layer to form an oxide region over the first sidewall of the sacrificial semiconductor layer and a germanium-enriched region within the sacrificial semiconductor layer and adjoined to the oxide region, wherein the germanium-enriched region has a second germanium concentration greater than the first germanium concentration;
forming a second trench opening extending through the dielectric material layer and the sacrificial semiconductor layer, wherein the second trench opening exposes a second sidewall of the sacrificial semiconductor layer opposite to the first sidewall;
removing the sacrificial semiconductor layer to provide a trench, wherein the trench exposes a sidewall of the germanium-enriched region;
forming a semiconductor barrier layer over the exposed sidewall of the germanium-enriched region;
growing a III-V compound semiconductor material within the trench and laterally outwards from a sidewall surface of the semiconductor barrier layer to provide a III-V compound semiconductor layer; and
removing a defect-containing region of the III-V compound semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first germanium concentration is from 20% to 25%, and the second germanium concentration is from 50% to 70%.

### Claim 3 (depends on 1)

The method of claim 1, wherein the defect-containing region is removed by an anisotropic etch.

### Claim 4 (depends on 3)

The method of claim 3, wherein the anisotropic etch also removes the semiconductor barrier layer, the germanium-enriched region and the oxide region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the sacrificial semiconductor layer is removed by a lateral etch, and the lateral etch comprises hydrogen peroxide or gaseous HCl.

### Claim 6 (depends on 1)

The method of claim 1, wherein said growing comprises an aspect ratio trapping process, and wherein the defect-containing region is formed adjacent the sidewall surface of the semiconductor barrier layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a dielectric liner over a top surface and sidewall surfaces of the sacrificial semiconductor layer prior to the forming the dielectric material layer, wherein the first trench opening also extends through the dielectric liner.

### Claim 8 (depends on 1)

The method of claim 1, further comprising removing the dielectric material layer after the removing the defect-containing region.

### Claim 9 (depends on 1)

The method of claim 1, further comprising providing a semiconductor layer over another region of the insulator layer, wherein the semiconductor layer comprises silicon, germanium, or silicon germanium, and the another region is masked by the dielectric material layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the forming the first trench opening comprises:
forming a first mask layer over the dielectric material layer;
patterning the first mask layer to provide a first opening extending through the first mask layer, wherein the first opening exposes a first end of the sacrificial semiconductor layer; and
removing portions of the dielectric material layer and the sacrificial semiconductor layer that are exposed by the first opening to provide the first trench opening.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing the first mask layer after the forming the oxide region and the Ge-enriched region.

### Claim 12 (depends on 11)

The method of claim 11, wherein the forming the second trench opening comprises:
forming a second mask layer over the dielectric material layer, the oxide region and the insulator layer, wherein the second mask layer completely fills the first trench opening;
patterning the second mask layer to provide a second opening extending through the second mask layer, wherein the second opening exposes a second end of the sacrificial semiconductor layer opposite to the first end; and
removing portions of the dielectric material layer and the sacrificial semiconductor layer that are exposed by the second opening to provide the second trench opening.

### Claim 13 (depends on 12)

The method of claim 12, further comprising removing the second mask layer after the removing the sacrificial semiconductor layer.