# US 9,437,424 B2 · High mobility power metal-oxide semiconductor field-effect transistors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,424 B2
- Document ID: US9437424B2
- Status: Granted
- Kind: B2
- Application number: 12/123,664
- Filed: 2008-05-20
- Published: 2008-09-11
- Granted: 2016-09-06
- Earliest claimed: 2005-12-22
- Assignees: Vishay-Siliconix
- Applicants: Deva Pattanayak; Kuo-In Chen; The-Tu Chau
- Inventors: Deva Pattanayak; Kuo-In Chen; The-Tu Chau
- Web page: https://patentgrep.com/patent/US9437424B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/40: Crystalline structures
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3258: {Crystal orientation}
- H10P 14/3466: {Crystal orientation}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.

## Claims

### Claim 1

A method comprising:
utilizing a silicon wafer having a surface orientation in a direction;
etching a trench in a (110) plane of said wafer, wherein said etching comprises etching a plurality of perpendicular trenches bounded by (100) planes;
forming first and second source regions adjacent to and parallel to each long edge of said trench; and
forming a gate structure in said trench between said first and second source regions.

### Claim 2 (depends on 1)

The method of claim 1 wherein said plurality of perpendicular trenches form closed cells.

### Claim 3

A trench MOSFET comprising:
a silicon wafer including a surface orientation in a direction;
a trench formed in said silicon wafer in a (110) plane;
a plurality of perpendicular trenches bounded by (110) planes;
first and second source regions adjacent to and parallel to each long edge of said trench; and
a gate structure in said trench between said first and second source regions.

### Claim 4 (depends on 3)

The trench MOSFET of claim 3 wherein said plurality of perpendicular trenches form closed cells.