# US 9,437,423 B2 · Method for fabricating an inter dielectric layer in semiconductor device

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- Number: US 9,437,423 B2
- Document ID: US9437423B2
- Status: Granted
- Kind: B2
- Application number: 14/059,756
- Filed: 2013-10-22
- Published: 2014-02-13
- Granted: 2016-09-06
- Earliest claimed: 2007-06-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Byung Soo Eun
- Web page: https://patentgrep.com/patent/US9437423B2

## CPC

- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10B 12/482: {Bit lines}
- H10P 50/642: {Chemical etching}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.

## Claims

### Claim 1

A method for fabricating an inter dielectric layer in a semiconductor device, comprising:
forming a bit line stack over a semiconductor substrate, the bit line stack comprising a barrier metal pattern, a conductive pattern, and a hard mask pattern, the hard mask pattern having two sides, wherein the barrier metal pattern, the conductive pattern and the hard mask pattern are sequentially stacked;
forming a bit line spacer on both sides of the bit line stack to expose a top surface of the hard mask pattern, the bit line spacer covers entirely both sides of the bit line stack;
supplying a high density plasma (HDP) deposition source to the bit line stack to form a primary liner HDP oxide layer on the bit line spacer while maintaining a bottom bias of an HDP chamber at less than 500 W during formation of the primary liner HDP oxide layer, wherein the primary liner HDP oxide layer covers both sides of the bit line spacer and a top surface of the hard mask pattern;
etching the primary liner HDP oxide layer to a predetermined thickness to form a secondary liner HDP oxide layer, wherein the secondary liner HDP entirely covers both sides of the bit line spacer while exposing the top surface of the hard mask pattern;
filling an area defined by adjacent bit line stacks where the secondary liner HDP oxide layer is formed with a flowable spin on dielectric (SOD) layer such that the SOD layer contacts the secondary liner HDP oxide layer; and,
curing the flowable SOD layer to form an oxide layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising preheating the bit line stack before forming the primary liner HDP oxide layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the preheating of the bit line stack comprises:
loading the semiconductor substrate into the HDP chamber; and
applying a predetermined source power to the HDP chamber while supplying oxygen (O2) gas, argon (Ar) gas, and helium (He) gas into the HDP chamber, wherein source power is applied from a top bias and a side bias of the HDP chamber while a bottom bias is not applied.

### Claim 4 (depends on 1)

The method of claim 1, wherein the HDP deposition source comprises a source gas comprising silane (SiH4) gas and oxygen (O2) gas, and an additive gas comprising helium (He) gas.

### Claim 5 (depends on 1)

The method of claim 1, comprising forming the primary liner HDP oxide layer to a thickness ranging from about 500 Å to about 600 Å.

### Claim 6 (depends on 1)

The method of claim 1, comprising forming the secondary liner HDP oxide layer using a fluorine-based etch gas.

### Claim 7 (depends on 1)

The method of claim 1, wherein the secondary liner HDP oxide layer is formed by etching the primary liner HDP oxide layer by an etching thickness ranging from about 150 Å to about 190 Å.

### Claim 8 (depends on 1)

The method of claim 1, wherein the flowable spin on dielectric (SOD) layer comprises polysilizane (PSZ).

### Claim 9 (depends on 1)

The method of claim 1, wherein the curing the flowable SOD layer comprises curing for about one hour while supplying 1 L of hydrogen (H2) gas and 2 L of oxygen (O2) gas at a temperature between about 450° C. and about 550° C.

### Claim 10 (depends on 1)

The method of claim 1, wherein a bending phenomenon of the bit line stack due to plasma charge is minimized by maintaining the bottom bias at less than 500 W.