# US 9,437,418 B2 · Method for forming spacers for a transistor gate

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- Number: US 9,437,418 B2
- Document ID: US9437418B2
- Status: Granted
- Kind: B2
- Application number: 14/551,849
- Filed: 2014-11-24
- Published: 2015-06-11
- Granted: 2016-09-06
- Earliest claimed: 2013-11-25
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat A L'energie Atomique Et Aux Ene Alt
- Inventors: Nicolas Posseme
- Web page: https://patentgrep.com/patent/US9437418B2

## CPC

- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/511: {for IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6508: {by exposure to a liquid}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place.

## Claims

### Claim 1

A method for forming spacers of a gate of a field effect transistor, the gate being situated above an active layer made from semiconductor material surmounting an insulating layer and a supporting substrate, the active layer, the insulating layer and the supporting substrate defining a stack of the silicon on insulator (SOI) type, comprising a step of forming a protective layer covering at least the gate of the transistor, the method comprising:
before the step of forming the protective layer, a step of forming a porous layer between the gate and the protective layer, the porous layer having a dielectric constant k equal to or less than that of silicon oxide (SiO2);
after the step of forming the protective layer, a step of etching the protective layer performed anisotropically so as to preserve residual portions of the protective layer solely at the flanks of the gate, these residual portions constituting protective spacers of the gate so as to uncover the porous layer outside the flanks of the gate;
a modification to the porous layer performed by ion penetration within the porous layer in order to form a modified layer, said modification of the porous layer being performed by means of a plasma, the ions of which penetrate the uncovered porous layer, said modification being carried out anisotropically and so as to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer situated on the flanks of the gate, the porous layer situated on the flanks of the gate being protected by the protective spacers and constituting porous spacers for the gate; and
at least one step of removing the modified layer by means of a selective etching of the modified layer vis-à-vis said semiconductor material of the active layer and the protective spacers protecting the porous layer situated on the flanks of the gate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the porous layer has a dielectric constant less than that of the protective spacers.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the etching the protective layer and the modification are performed during a single step during which the ions used for etching the protective layer modify the porous layer in order to form the modified layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the etching the protective layer is performed by means of a plasma based on argon (Ar), oxygen (O2) or nitrogen (N2).

### Claim 5 (depends on 1)

The method according to claim 1, wherein the plasma used for the modification of the porous layer is based on argon (Ar), oxygen (O2) or nitrogen (N2).

### Claim 6 (depends on 1)

The method according to claim 1, wherein the step of forming the protective layer is performed in order to form a protective layer, with a thickness of between 2 manometers (nm) and 3 nm.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the step of forming the porous layer is performed in order to form a porous layer with a thickness of less than 20 nm, and the modification of the porous layer performed by means of a plasma is carried so as to implement the porous layer continuously from the surface of the porous layer through which the ions of the plasma penetrate.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the modification step carried out using a plasma modifies the porous layer continuously from the surface of the porous layer and over a thickness of between 1 nm and 30 nm.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the step of forming the porous layer is carried out in order to form a porous layer with a thickness of between 5 nm and 6 nm.

### Claim 10 (depends on 1)

The method according to claim 1, wherein, on either side of the gate, the porous layer is disposed directly in contact with the active layer.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the active layer as a thickness of less than 30 nm.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the step of forming the porous layer is performed by a plasma assisted chemical vapour deposition (PECVD) method.

### Claim 13 (depends on 1)

The method according to claim 1, wherein the material of the protective layer is chosen so as to resist the selective etching carried out at the step of removing the modified layer.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the protective layer is a layer of nitride such as a layer of silicon nitride.

### Claim 15 (depends on 1)

The method according to claim 1, wherein the protective layer is a layer of boron nitride (BN), SiO2, non-porous SiOCH or SiCBN.

### Claim 16 (depends on 1)

The method according to claim 1, wherein the porous layer is a layer of porous SiOCH.

### Claim 17 (depends on 1)

The method according to claim 1, wherein the dielectric constant of the porous layer is between 2.1 and 3, and preferably equal to or less than that of porous SiOCH.

### Claim 18 (depends on 1)

The method according to claim 1, wherein the modified layer is formed by porous silicon oxide (SiO2).

### Claim 19 (depends on 1)

The method according to claim 1, wherein the step of removing the modified layer is carried out by wet etching selective with respect to said semiconductor material of the active layer.

### Claim 20 (depends on 1)

The method according to claim 1, wherein the semiconductor material is silicon and wherein the step of removing the modified layer is performed by wet etching selectively with respect to silicon (Si) using a solution based on hydrofluoric acid (HF).

### Claim 21 (depends on 1)

The method according to claim 1, wherein the semiconductor material is silicon and wherein the step of removing the modified layer is performed by dry etching selective with respect to silicon (Si), the dry etching being carried in a plasma based on nitrogen trifluoride (NF3) and ammonia (NH3).

### Claim 22 (depends on 21)

The method according to claim 21, wherein the dry etching comprises:
an etching step consisting of the formation of solid salts:
a step of sublimation of the solid species.

### Claim 23 (depends on 1)

The method according to claim 1, wherein said modification made so as to modify the porous layer throughout its thickness over all-surfaces parallel to a plane of the substrate on which the gate rests and so as not to modify the porous layer throughout its thickness on the surfaces perpendicular to this plane.

### Claim 24 (depends on 1)

The method according to claim 1, wherein the step of removing the modified layer is performed so as to preserve the porous layer on the flanks of the gate.

### Claim 25 (depends on 1)

The method according to claim 1, wherein the transistor is an FDSOI transistor.

### Claim 26 (depends on 1)

The method according to claim 1, wherein the transistor is a FinFET transistor.

### Claim 27 (depends on 1)

The method according to claim 1, comprising, after the step of removing the modified layer, a step of removing the protective spacers covering the flanks of the gate, obtained by etching using a solution based on phosphoric acid (H3PO4).

### Claim 28 (depends on 7)

The method according to claim 7, wherein the step of forming the porous layer is performed in order to form a porous layer with a thickness of less than 10 nm.

### Claim 29 (depends on 8)

The method according to claim 8, wherein the modification step carried out using a plasma modifies the porous layer continuously from the surface of the porous layer and over a thickness of between 1 nm and 10 nm.

### Claim 30 (depends on 11)

The method according to claim 11, wherein the active layer has a thickness of less than 20 nm.