# US 9,437,417 B2 · Low temperature polycrystalline silicon thin film and method of producing the same, array substrate and display apparatus

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- Number: US 9,437,417 B2
- Document ID: US9437417B2
- Status: Granted
- Kind: B2
- Application number: 14/081,833
- Filed: 2013-11-15
- Published: 2014-05-22
- Granted: 2016-09-06
- Earliest claimed: 2012-11-22
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Xueyan Tian; Chunping Long
- Web page: https://patentgrep.com/patent/US9437417B2

## CPC

- H10D 86/0227: {using structural arrangements to control crystal growth, e.g. placement of grain filters}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/3238: {being insulating materials}
- H10P 14/3241: {being conductive materials}
- H10P 14/3242: {Structure}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/3806: {using crystallisation-enhancing elements}
- H10P 14/3816: {Pulsed laser beam}
- H10P 14/68: Organic materials, e.g. photoresists
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.

## Claims

### Claim 1

A method for producing a low temperature polycrystalline silicon thin film, comprising steps of:
providing a substrate;
forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and
performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film,
wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate, and
wherein said step of performing the high-temperature treatment and the laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film comprising steps of:
performing a high-temperature treatment on the amorphous silicon layer at a temperature of 400˜500° C. for a period of 0.5˜3 hours; and
performing an excimer laser annealing on the amorphous silicon layer processed by the high-temperature treatment with a laser having a pulse frequency of 300 Hz, an overlapping coefficient of 92%˜98%, and an energy density of 200˜500 mJ/cm2; and
wherein during the laser annealing, the amorphous silicon thin film is cooled more quickly in a first area with the patterns of the thermal conduction and electrical insulation layer than a second area without the patterns of the thermal conduction and electrical insulation layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the thermal conduction and electrical insulation layer is made of any one of aluminum nitride, boron nitride, aluminum oxide, and magnesium oxide.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the thermal conduction and electrical insulation layer comprises circular patterns, rectangular patterns or strip patterns evenly distributed on the substrate.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the circular pattern, the rectangular pattern or the strip pattern has a size within a range of 0.1 μm˜1 μm.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the size of the circular pattern, the rectangular pattern or the strip pattern is set as 0.5 μm.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the thermal conduction and electrical insulation layer is formed by spray coating, or by magnetron sputtering and exposure etching.

### Claim 7 (depends on 1)

A thin film transistor, comprising an active layer formed by a polycrystalline silicon thin film, wherein the polycrystalline silicon thin film is produced by a method according to claim 1.

### Claim 8 (depends on 7)

The thin film transistor according to claim 7, wherein the buffer layer and the thermal conduction and electrical insulation layer are formed below the active layer of the thin film transistor.

### Claim 9 (depends on 7)

An array substrate comprising the thin film transistor according to claim claim 7.

### Claim 10 (depends on 9)

A display apparatus comprising the array substrate according to claim 9.