# US 9,437,330 B2 · Memory device and memory system include hard repair mode and soft repair mode > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,330 B2 - Document ID: US9437330B2 - Status: Granted - Kind: B2 - Application number: 14/571,047 - Filed: 2014-12-15 - Published: 2016-03-17 - Granted: 2016-09-06 - Earliest claimed: 2014-09-11 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Ga-Ram Park; Jong-Yeol Yang - Web page: https://patentgrep.com/patent/US9437330B2 ## CPC - G11C 29/78: {using programmable devices} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 29/4401: {for self repair} - G11C 2029/0409: {Online test} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers. ## Claims ### Claim 1 A memory device, comprising: a non-volatile memory circuit configure to store hard repair data; a data bus configure to transmit the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers configure to store repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit configure to select a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank configure to perform a repair operation based on the data stored in a register that is activated among the plurality of the registers. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the control circuit sequentially selects the plurality of the registers during the boot-up operation, and wherein, during the soft repair mode, the control circuit selects a register that does not store data after the boot-up operation is completed. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the control circuit compares the transmitted repair data with the data stored in the plurality of the registers during the soft repair mode, and wherein the control circuit compares an external address inputted from an exterior of the memory device with the data stored in the plurality of the registers during the repair operation. ### Claim 4 (depends on 1) The memory device of claim 1, wherein, in the soft repair mode, the control circuit deactivates a register storing the same data as the transmitted repair data in response to an active command, and stores the transmitted repair data in a selected register among the plurality of the registers in response to a write command. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the non-volatile memory circuit includes one-time programmable memory cells in which data are not changed once the data are stored. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the data stored in the non-volatile memory circuit are retained permanently, and the data stored in the plurality of the registers are erased when the memory device is turned off. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the hard repair data includes memory hard repair data, which is repair data programmed when the memory device is fabricated, and system hard repair data, which is repair data transmitted from a memory controller to the memory device, and wherein the soft repair data is repair data transmitted from the memory controller to the memory device. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the plurality of the registers include: one or more memory registers for storing the memory hard repair data; and one or more system registers for storing the system hard repair data or the soft repair data. ### Claim 9 A memory device, comprising: a non-volatile memory circuit including memory regions for storing memory hard repair data of memory banks and system regions for storing system hard repair data of the memory banks; a data bus configure to transmit the memory hard repair data and the system hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; registers configure to store data of a corresponding memory bank among the repair data transmitted through the data bus and activating when the transmitted repair data are stored; a control circuit configure to select a register to store the transmitted repair data among the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data among the registers corresponding to a memory bank corresponding to the transmitted repair data; and memory banks configure to perform a repair operation based on the data stored in activated registers. ### Claim 10 (depends on 9) The memory device of claim 9, wherein the control circuit sequentially selects the registers during the boot-up operation, and wherein, during the soft repair mode, the control circuit selects a register that does not store data after the boot-up operation is completed among the registers corresponding to the transmitted repair data. ### Claim 11 (depends on 9) The memory device of claim 9, wherein the control circuit compares the transmitted repair data with the data stored in the registers corresponding to a memory bank corresponding to the transmitted repair data during the soft repair mode, and wherein the control circuit compares an external address inputted from an exterior of the memory device with the data stored in the registers corresponding to a memory bank designated by the inputted address during the repair operation. ### Claim 12 (depends on 9) The memory device of claim 9, wherein the data stored in the non-volatile memory circuit are retained permanently, and the data stored in the registers are erased when the memory device is turned off. ### Claim 13 (depends on 9) The memory device of claim 9, wherein the memory hard repair data is repair data programmed when the memory device is fabricated, and wherein the system hard repair data and the soft repair data are repair data transmitted from a memory controller to the memory device. ### Claim 14 (depends on 13) The memory device of claim 13, wherein the registers include: one or more memory registers for storing the memory hard repair data; and one or more system registers for storing the system hard repair data or the soft repair data. ### Claim 15 (depends on 9) The memory device of claim 9, wherein the non-volatile memory circuit includes one-time programmable memory cells in which data are not changed once the data are stored. ### Claim 16 (depends on 9) The memory device of claim 9, wherein, when a bank address and a normal address are inputted in a hard repair mode, the normal address is programmed in a system region selected based on the bank address among the system regions, and wherein, when the bank address and the normal address are inputted in a soft repair mode, the normal address is programmed in the registers corresponding to a memory bank designated by the bank address among the registers. ### Claim 17 (depends on 9) The memory device of claim 9, wherein the memory regions include first to Nth memory regions, wherein the system regions include first to Nth system regions, wherein the registers include first to Nth registers, wherein the memory banks include first to Nth memory banks, wherein the first to Nth the memory banks correspond to the first to Nth memory regions, the first to Nth system regions and the first to Nth registers, respectively. ### Claim 18 A memory system, comprising: a memory device that comprises: a non-volatile memory circuit; memory banks, wherein the memory device programs system hard repair data inputted in a hard repair mode in the non-volatile memory circuit and performs a repair operation based on the repair data stored in the non-volatile memory circuit and soft repair data inputted in a soft repair mode; and a memory controller configure to set up the memory device in the hard repair mode or the soft repair mode, inputting the system hard repair data into the memory device in the hard repair mode, and inputting the soft repair data into the memory device in the soft repair mode, wherein the memory device further comprises: a data bus that transmits, memory hard repair data and the system hard repair data during a boot-up operation, and transmits the soft repair data during a soft repair mode; registers that store data of a corresponding memory bank among the repair data transmitted through the data bus, the registers being activated when the transmitted repair data are stored; and a control circuit that selects a register to store the transmitted repair data among the registers, and during the soft repair mode, deactivates a register storing the same data as the transmitted repair data among the registers corresponding to a memory bank corresponding to the transmitted repair data. ### Claim 19 (depends on 18) The memory system of claim 18, wherein the memory device performs repair operations of the memory banks based on the data stored in the activated register among the registers. ### Claim 20 (depends on 18) The memory system of claim 18, wherein the memory hard repair data is programmed when the memory device is fabricated. ### Claim 21 (depends on 18) The memory system of claim 18, wherein the non-volatile memory circuit includes one-time programmable memory cells in which data are not changed once the data are stored. ### Claim 22 (depends on 18) The memory system of claim 18, wherein the memory device further comprises: registers suitable for storing hard repair data including the system hard repair data and the soft repair data, wherein each of the registers is activated when one of the hard repair data and the soft repair data is stored therein; a control circuit suitable for control the registers to store the hard repair data during a boot-up operation, and to store the soft repair data in a soft repair mode, wherein the control circuit in the soft repair mode deactivates one or more hard repair registers of the registers storing the hard repair data, which is the same as the soft repair data; and a memory bank suitable for performing a repair operation based on the hard repair data and the soft repair data stored in activated registers of the registers. ### Claim 23 (depends on 22) The memory system of claim 22, wherein, in the soft repair mode, the control circuit controls one or more soft repair registers of the registers, which are empty after the boot-up operation, to store the soft repair data. ### Claim 24 (depends on 23) The memory system of claim 23, wherein, in the soft repair mode, the control circuit deactivates the hard repair registers in response to an active command, and controls the soft repair registers to store the soft repair data in response to a write command. ### Claim 25 (depends on 22) The memory system of claim 22, wherein the registers are initialized when the memory device is turned off. ### Claim 26 (depends on 22) The memory system of claim 22, wherein the hard repair data is permanently stored in the memory system in fabrication, and wherein the soft repair data is temporarily stored in the memory device in operation. ### Claim 27 A memory device, comprising: registers configure to store hard repair data and soft repair data, wherein each of the registers is activated when one of the hard repair data and the soft repair data is stored therein; a control circuit configure to control the registers to store the hard repair data during a boot-up operation, and to store the soft repair data in a soft repair mode, wherein the control circuit in the soft repair mode deactivates one or more hard repair registers of the registers storing the hard repair data, which is the same as the soft repair data; and a memory bank configure to perform a repair operation based on the hard repair data and the soft repair data stored in activated registers of the registers. ### Claim 28 (depends on 27) The memory device of claim 27, wherein, in the soft repair mode, the control circuit controls one or more soft repair registers of the registers, which are empty after the boot-up operation, to store the soft repair data. ### Claim 29 (depends on 28) The memory device of claim 28, wherein, in the soft repair mode, the control circuit deactivates the hard repair registers in response to an active command, and controls the soft repair registers to store the soft repair data in response to a write command. ### Claim 30 (depends on 27) The memory device of claim 27, wherein the registers are initialized when the memory device is turned off. ### Claim 31 (depends on 27) The memory device of claim 27, wherein the hard repair data is permanently stored in the memory device in fabrication, and wherein the soft repair data is temporarily stored in the memory device in operation.