# US 9,437,329 B2 · Semiconductor device with initialization operation and boot-up operation

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- Number: US 9,437,329 B2
- Document ID: US9437329B2
- Status: Granted
- Kind: B2
- Application number: 14/533,861
- Filed: 2014-11-05
- Published: 2016-01-14
- Granted: 2016-09-06
- Earliest claimed: 2014-07-09
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ga-Ram Park
- Web page: https://patentgrep.com/patent/US9437329B2

## CPC

- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 2229/743: After packaging
- G11C 2229/763: E-fuses, e.g. electric fuses or antifuses, floating gate transistors
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device includes: a first block, which is initialized during an initialization mode; and a second block, which is initialized while the first block latches first signals during a boot-up mode. Herein, the second block may latch second signals after being initialized during the boot-up mode.

## Claims

### Claim 1

A semiconductor device, comprising:
a first block, which is initialized during an initialization mode; and
a second block, which is subsequently initialized while the first block latches first signals during a boot-up mode, wherein an initialization operation of the second block is performed while a boot-up operation is performed on the first block,
wherein the boot-up operation of the second block is performed in response to a first bank selection signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second block latches second signals after being initialized during the boot-up mode.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a third block, which is initialized while the second block latches the second signals during the boot-up mode,
wherein the third block latches third signals after being initialized during the boot-up mode.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first to third signals include fuse signals.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first latch block and the second block are formed in a core region and the first signals are from a peripheral region.

### Claim 6

A semiconductor device, comprising:
first and second memory regions;
a first block, which is formed corresponding to the first memory region, and which is initialized in response to an initialization signal during an initialization mode; and
a second block, which is formed corresponding to the second memory region, and which is subsequently initialized in response to a boot-up mode signal and a first region selection signal for selecting the first memory region during a boot-up mode, wherein an initialization operation of the second block is performed while a boot-up operation is performed on the first block,
wherein the first and second memory regions and the first and second latch blocks are formed in a core region and the fuse block are from a peripheral region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a fuse block suitable for transmitting first fuse signals to the first block in response to the first region selection signal, and transmitting second fuse signals to the second block in response to a second region selection signal for selecting the second memory region.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first and second region selection signals are sequentially enabled.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, further comprising:
third to nth memory regions; and
third to nth blocks, which are formed respectively corresponding to the third to nth memory regions, and which are initialized in response to the boot-up mode signal and second to (n−1)th region selection signals for selecting the second to (n−1)th memory regions during the boot-up mode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a fuse block suitable for sequentially transmitting first to nth fuse signals to the first to nth blocks for each of the first to nth memory regions in response to the first to (n−1)th region selection signals and a nth region selection signal for selecting the nth memory region during the boot-up mode.

### Claim 11

A method for driving a semiconductor device, comprising:
initializing a first latch block;
subsequently initializing a second latch block while the first latch block performs a boot-up operation; and
performing the boot-up operation of the second latch block,
wherein an initialization operation of the second latch block and the boot-up operation of the first latch block are performed at the same time, and
wherein the boot-up operation of the second latch block is performed in response to a first bank selection signal.

### Claim 12 (depends on 11)

The method of claim 11,
wherein the first latch block performs the boot-up operation by latching first fuse signals, and
wherein the performing the boot-up operation of the second latch block latches second fuse signals in the second latch block.

### Claim 13 (depends on 11)

The method of claim 11, further comprising sequentially performing the boot-up operation of third to nth latch blocks after the first and second latch blocks perform the boot-up operation,
wherein the third to nth latch blocks are sequentially initialized while the second to (n−1)th latch blocks sequentially perform the boot-up operation.