# US 9,437,327 B2 · Combined rank and linear address incrementing utility for computer memory test operations

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,327 B2
- Document ID: US9437327B2
- Status: Granted
- Kind: B2
- Application number: 15/063,727
- Filed: 2016-03-08
- Published: 2016-06-16
- Granted: 2016-09-06
- Earliest claimed: 2014-03-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Lawrence D. Curley; Patrick J. Meaney; George C. Wellwood
- Web page: https://patentgrep.com/patent/US9437327B2

## CPC

- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection}
- G06F 11/2635: {using a storage for the test inputs, e.g. test ROM, script files}
- G06F 12/0607: {Interleaved addressing}
- G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C 29/20: using counters or linear-feedback shift registers [LFSR]
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 2029/0409: {Online test}
- G11C 2029/1806: {Address conversion or mapping, i.e. logical to physical address}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

## Claims

### Claim 1

A combined rank and linear address incrementing utility for a computer system, comprising:
a memory address map register configured to selectively store memory address maps for a plurality of different types of memory configurations;
a rank register configured to store a plurality of rank address bits mapped from the memory address map register corresponding to one or more rank address fields of the memory address map register, wherein the rank register maps to rank address fields of the selected memory address register that are not contiguous;
a non-rank register configured to store a plurality of non-rank address bits mapped from the memory address map register corresponding to one or more non-rank address fields of the memory address map register, wherein the non-rank register maps to non-rank address fields of the selected memory address register that are not contiguous;
a selected address register configured to define a range of selected memory addresses within the selected address register based on a sequence of bits mapped from the rank register and the non-rank register;
a control register for selectively setting the utility in a linear mode or a rank mode; and
increment logic configured to increment the rank register and the non-rank register to sequentially generate ranges of addresses corresponding to address spaces of the different memory configurations for testing those memory configurations,
wherein the increment logic is further configured to selectively operate in the linear mode for generating addresses corresponding to a selected rank, or in the rank mode for generating addresses corresponding to a plurality of ranks on a rank-by-rank basis.